MINI Sh3ll

Path : /lib/modules/5.15.0-43-generic/build/arch/mips/include/asm/mach-ath79/
File Upload :
Current File : //lib/modules/5.15.0-43-generic/build/arch/mips/include/asm/mach-ath79/ar71xx_regs.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  Atheros AR71XX/AR724X/AR913X SoC register definitions
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
 *  Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
 *  Copyright (C) 2008 Imre Kaloz <[email protected]>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 */

#ifndef __ASM_MACH_AR71XX_REGS_H
#define __ASM_MACH_AR71XX_REGS_H

#include <linux/types.h>
#include <linux/io.h>
#include <linux/bitops.h>

#define AR71XX_APB_BASE		0x18000000
#define AR71XX_GE0_BASE		0x19000000
#define AR71XX_GE0_SIZE		0x10000
#define AR71XX_GE1_BASE		0x1a000000
#define AR71XX_GE1_SIZE		0x10000
#define AR71XX_EHCI_BASE	0x1b000000
#define AR71XX_EHCI_SIZE	0x1000
#define AR71XX_OHCI_BASE	0x1c000000
#define AR71XX_OHCI_SIZE	0x1000
#define AR71XX_SPI_BASE		0x1f000000
#define AR71XX_SPI_SIZE		0x01000000

#define AR71XX_DDR_CTRL_BASE	(AR71XX_APB_BASE + 0x00000000)
#define AR71XX_DDR_CTRL_SIZE	0x100
#define AR71XX_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
#define AR71XX_UART_SIZE	0x100
#define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
#define AR71XX_USB_CTRL_SIZE	0x100
#define AR71XX_GPIO_BASE	(AR71XX_APB_BASE + 0x00040000)
#define AR71XX_GPIO_SIZE	0x100
#define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
#define AR71XX_PLL_SIZE		0x100
#define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE	0x100
#define AR71XX_MII_BASE		(AR71XX_APB_BASE + 0x00070000)
#define AR71XX_MII_SIZE		0x100

#define AR71XX_PCI_MEM_BASE	0x10000000
#define AR71XX_PCI_MEM_SIZE	0x07000000

#define AR71XX_PCI_WIN0_OFFS	0x10000000
#define AR71XX_PCI_WIN1_OFFS	0x11000000
#define AR71XX_PCI_WIN2_OFFS	0x12000000
#define AR71XX_PCI_WIN3_OFFS	0x13000000
#define AR71XX_PCI_WIN4_OFFS	0x14000000
#define AR71XX_PCI_WIN5_OFFS	0x15000000
#define AR71XX_PCI_WIN6_OFFS	0x16000000
#define AR71XX_PCI_WIN7_OFFS	0x07000000

#define AR71XX_PCI_CFG_BASE	\
	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
#define AR71XX_PCI_CFG_SIZE	0x100

#define AR7240_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
#define AR7240_USB_CTRL_SIZE	0x100
#define AR7240_OHCI_BASE	0x1b000000
#define AR7240_OHCI_SIZE	0x1000

#define AR724X_PCI_MEM_BASE	0x10000000
#define AR724X_PCI_MEM_SIZE	0x04000000

#define AR724X_PCI_CFG_BASE	0x14000000
#define AR724X_PCI_CFG_SIZE	0x1000
#define AR724X_PCI_CRP_BASE	(AR71XX_APB_BASE + 0x000c0000)
#define AR724X_PCI_CRP_SIZE	0x1000
#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
#define AR724X_PCI_CTRL_SIZE	0x100

#define AR724X_EHCI_BASE	0x1b000000
#define AR724X_EHCI_SIZE	0x1000

#define AR913X_EHCI_BASE	0x1b000000
#define AR913X_EHCI_SIZE	0x1000
#define AR913X_WMAC_BASE	(AR71XX_APB_BASE + 0x000C0000)
#define AR913X_WMAC_SIZE	0x30000

#define AR933X_UART_BASE	(AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE	0x14
#define AR933X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
#define AR933X_GMAC_SIZE	0x04
#define AR933X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define AR933X_WMAC_SIZE	0x20000
#define AR933X_EHCI_BASE	0x1b000000
#define AR933X_EHCI_SIZE	0x1000

#define AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
#define AR934X_GMAC_SIZE	0x14
#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE	0x20000
#define AR934X_EHCI_BASE	0x1b000000
#define AR934X_EHCI_SIZE	0x200
#define AR934X_NFC_BASE		0x1b000200
#define AR934X_NFC_SIZE		0xb8
#define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
#define AR934X_SRIF_SIZE	0x1000

#define QCA953X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
#define QCA953X_GMAC_SIZE	0x14
#define QCA953X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define QCA953X_WMAC_SIZE	0x20000
#define QCA953X_EHCI_BASE	0x1b000000
#define QCA953X_EHCI_SIZE	0x200
#define QCA953X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
#define QCA953X_SRIF_SIZE	0x1000

#define QCA953X_PCI_CFG_BASE0	0x14000000
#define QCA953X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
#define QCA953X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
#define QCA953X_PCI_MEM_BASE0	0x10000000
#define QCA953X_PCI_MEM_SIZE	0x02000000

#define QCA955X_PCI_MEM_BASE0	0x10000000
#define QCA955X_PCI_MEM_BASE1	0x12000000
#define QCA955X_PCI_MEM_SIZE	0x02000000
#define QCA955X_PCI_CFG_BASE0	0x14000000
#define QCA955X_PCI_CFG_BASE1	0x16000000
#define QCA955X_PCI_CFG_SIZE	0x1000
#define QCA955X_PCI_CRP_BASE0	(AR71XX_APB_BASE + 0x000c0000)
#define QCA955X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
#define QCA955X_PCI_CRP_SIZE	0x1000
#define QCA955X_PCI_CTRL_BASE0	(AR71XX_APB_BASE + 0x000f0000)
#define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
#define QCA955X_PCI_CTRL_SIZE	0x100

#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
#define QCA955X_GMAC_SIZE	0x40
#define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define QCA955X_WMAC_SIZE	0x20000
#define QCA955X_EHCI0_BASE	0x1b000000
#define QCA955X_EHCI1_BASE	0x1b400000
#define QCA955X_EHCI_SIZE	0x1000
#define QCA955X_NFC_BASE	0x1b800200
#define QCA955X_NFC_SIZE	0xb8

#define QCA956X_PCI_MEM_BASE1	0x12000000
#define QCA956X_PCI_MEM_SIZE	0x02000000
#define QCA956X_PCI_CFG_BASE1	0x16000000
#define QCA956X_PCI_CFG_SIZE	0x1000
#define QCA956X_PCI_CRP_BASE1	(AR71XX_APB_BASE + 0x00250000)
#define QCA956X_PCI_CRP_SIZE	0x1000
#define QCA956X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
#define QCA956X_PCI_CTRL_SIZE	0x100

#define QCA956X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
#define QCA956X_WMAC_SIZE	0x20000
#define QCA956X_EHCI0_BASE	0x1b000000
#define QCA956X_EHCI1_BASE	0x1b400000
#define QCA956X_EHCI_SIZE	0x200
#define QCA956X_GMAC_SGMII_BASE	(AR71XX_APB_BASE + 0x00070000)
#define QCA956X_GMAC_SGMII_SIZE	0x64
#define QCA956X_PLL_BASE	(AR71XX_APB_BASE + 0x00050000)
#define QCA956X_PLL_SIZE	0x50
#define QCA956X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
#define QCA956X_GMAC_SIZE	0x64

/*
 * Hidden Registers
 */
#define QCA956X_MAC_CFG_BASE		0xb9000000
#define QCA956X_MAC_CFG_SIZE		0x64

#define QCA956X_MAC_CFG1_REG		0x00
#define QCA956X_MAC_CFG1_SOFT_RST	BIT(31)
#define QCA956X_MAC_CFG1_RX_RST		BIT(19)
#define QCA956X_MAC_CFG1_TX_RST		BIT(18)
#define QCA956X_MAC_CFG1_LOOPBACK	BIT(8)
#define QCA956X_MAC_CFG1_RX_EN		BIT(2)
#define QCA956X_MAC_CFG1_TX_EN		BIT(0)

#define QCA956X_MAC_CFG2_REG		0x04
#define QCA956X_MAC_CFG2_IF_1000	BIT(9)
#define QCA956X_MAC_CFG2_IF_10_100	BIT(8)
#define QCA956X_MAC_CFG2_HUGE_FRAME_EN	BIT(5)
#define QCA956X_MAC_CFG2_LEN_CHECK	BIT(4)
#define QCA956X_MAC_CFG2_PAD_CRC_EN	BIT(2)
#define QCA956X_MAC_CFG2_FDX		BIT(0)

#define QCA956X_MAC_MII_MGMT_CFG_REG	0x20
#define QCA956X_MGMT_CFG_CLK_DIV_20	0x07

#define QCA956X_MAC_FIFO_CFG0_REG	0x48
#define QCA956X_MAC_FIFO_CFG1_REG	0x4c
#define QCA956X_MAC_FIFO_CFG2_REG	0x50
#define QCA956X_MAC_FIFO_CFG3_REG	0x54
#define QCA956X_MAC_FIFO_CFG4_REG	0x58
#define QCA956X_MAC_FIFO_CFG5_REG	0x5c

#define QCA956X_DAM_RESET_OFFSET	0xb90001bc
#define QCA956X_DAM_RESET_SIZE		0x4
#define QCA956X_INLINE_CHKSUM_ENG	BIT(27)

/*
 * DDR_CTRL block
 */
#define AR71XX_DDR_REG_PCI_WIN0		0x7c
#define AR71XX_DDR_REG_PCI_WIN1		0x80
#define AR71XX_DDR_REG_PCI_WIN2		0x84
#define AR71XX_DDR_REG_PCI_WIN3		0x88
#define AR71XX_DDR_REG_PCI_WIN4		0x8c
#define AR71XX_DDR_REG_PCI_WIN5		0x90
#define AR71XX_DDR_REG_PCI_WIN6		0x94
#define AR71XX_DDR_REG_PCI_WIN7		0x98
#define AR71XX_DDR_REG_FLUSH_GE0	0x9c
#define AR71XX_DDR_REG_FLUSH_GE1	0xa0
#define AR71XX_DDR_REG_FLUSH_USB	0xa4
#define AR71XX_DDR_REG_FLUSH_PCI	0xa8

#define AR724X_DDR_REG_FLUSH_GE0	0x7c
#define AR724X_DDR_REG_FLUSH_GE1	0x80
#define AR724X_DDR_REG_FLUSH_USB	0x84
#define AR724X_DDR_REG_FLUSH_PCIE	0x88

#define AR913X_DDR_REG_FLUSH_GE0	0x7c
#define AR913X_DDR_REG_FLUSH_GE1	0x80
#define AR913X_DDR_REG_FLUSH_USB	0x84
#define AR913X_DDR_REG_FLUSH_WMAC	0x88

#define AR933X_DDR_REG_FLUSH_GE0	0x7c
#define AR933X_DDR_REG_FLUSH_GE1	0x80
#define AR933X_DDR_REG_FLUSH_USB	0x84
#define AR933X_DDR_REG_FLUSH_WMAC	0x88

#define AR934X_DDR_REG_FLUSH_GE0	0x9c
#define AR934X_DDR_REG_FLUSH_GE1	0xa0
#define AR934X_DDR_REG_FLUSH_USB	0xa4
#define AR934X_DDR_REG_FLUSH_PCIE	0xa8
#define AR934X_DDR_REG_FLUSH_WMAC	0xac

#define QCA953X_DDR_REG_FLUSH_GE0	0x9c
#define QCA953X_DDR_REG_FLUSH_GE1	0xa0
#define QCA953X_DDR_REG_FLUSH_USB	0xa4
#define QCA953X_DDR_REG_FLUSH_PCIE	0xa8
#define QCA953X_DDR_REG_FLUSH_WMAC	0xac

/*
 * PLL block
 */
#define AR71XX_PLL_REG_CPU_CONFIG	0x00
#define AR71XX_PLL_REG_SEC_CONFIG	0x04
#define AR71XX_PLL_REG_ETH0_INT_CLOCK	0x10
#define AR71XX_PLL_REG_ETH1_INT_CLOCK	0x14

#define AR71XX_PLL_FB_SHIFT		3
#define AR71XX_PLL_FB_MASK		0x1f
#define AR71XX_CPU_DIV_SHIFT		16
#define AR71XX_CPU_DIV_MASK		0x3
#define AR71XX_DDR_DIV_SHIFT		18
#define AR71XX_DDR_DIV_MASK		0x3
#define AR71XX_AHB_DIV_SHIFT		20
#define AR71XX_AHB_DIV_MASK		0x7

#define AR71XX_ETH0_PLL_SHIFT		17
#define AR71XX_ETH1_PLL_SHIFT		19

#define AR724X_PLL_REG_CPU_CONFIG	0x00
#define AR724X_PLL_REG_PCIE_CONFIG	0x10

#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS	BIT(16)
#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET	BIT(25)

#define AR724X_PLL_FB_SHIFT		0
#define AR724X_PLL_FB_MASK		0x3ff
#define AR724X_PLL_REF_DIV_SHIFT	10
#define AR724X_PLL_REF_DIV_MASK		0xf
#define AR724X_AHB_DIV_SHIFT		19
#define AR724X_AHB_DIV_MASK		0x1
#define AR724X_DDR_DIV_SHIFT		22
#define AR724X_DDR_DIV_MASK		0x3

#define AR7242_PLL_REG_ETH0_INT_CLOCK	0x2c

#define AR913X_PLL_REG_CPU_CONFIG	0x00
#define AR913X_PLL_REG_ETH_CONFIG	0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK	0x14
#define AR913X_PLL_REG_ETH1_INT_CLOCK	0x18

#define AR913X_PLL_FB_SHIFT		0
#define AR913X_PLL_FB_MASK		0x3ff
#define AR913X_DDR_DIV_SHIFT		22
#define AR913X_DDR_DIV_MASK		0x3
#define AR913X_AHB_DIV_SHIFT		19
#define AR913X_AHB_DIV_MASK		0x1

#define AR913X_ETH0_PLL_SHIFT		20
#define AR913X_ETH1_PLL_SHIFT		22

#define AR933X_PLL_CPU_CONFIG_REG	0x00
#define AR933X_PLL_CLOCK_CTRL_REG	0x08

#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
#define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT	16
#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT	23
#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7

#define AR933X_PLL_CLOCK_CTRL_BYPASS		BIT(2)
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT	5
#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK	0x3
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT	10
#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK	0x3
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7

#define AR934X_PLL_CPU_CONFIG_REG		0x00
#define AR934X_PLL_DDR_CONFIG_REG		0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
#define AR934X_PLL_ETH_XMII_CONTROL_REG		0x2c

#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
#define AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3

#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
#define AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7

#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	BIT(2)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	BIT(3)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	BIT(4)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)

#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)

#define QCA953X_PLL_CPU_CONFIG_REG		0x00
#define QCA953X_PLL_DDR_CONFIG_REG		0x04
#define QCA953X_PLL_CLK_CTRL_REG		0x08
#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG	0x24
#define QCA953X_PLL_ETH_XMII_CONTROL_REG	0x2c
#define QCA953X_PLL_ETH_SGMII_CONTROL_REG	0x48

#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT	6
#define QCA953X_PLL_CPU_CONFIG_NINT_MASK	0x3f
#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK	0x7

#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT	10
#define QCA953X_PLL_DDR_CONFIG_NINT_MASK	0x3f
#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7

#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)

#define QCA955X_PLL_CPU_CONFIG_REG		0x00
#define QCA955X_PLL_DDR_CONFIG_REG		0x04
#define QCA955X_PLL_CLK_CTRL_REG		0x08
#define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
#define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
#define QCA955X_PLL_ETH_SGMII_SERDES_REG	0x4c

#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT	6
#define QCA955X_PLL_CPU_CONFIG_NINT_MASK	0x3f
#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3

#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT	10
#define QCA955X_PLL_DDR_CONFIG_NINT_MASK	0x3f
#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7

#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL		BIT(20)
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL		BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)

#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT	BIT(2)
#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK		BIT(1)
#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL		BIT(0)

#define QCA956X_PLL_CPU_CONFIG_REG			0x00
#define QCA956X_PLL_CPU_CONFIG1_REG			0x04
#define QCA956X_PLL_DDR_CONFIG_REG			0x08
#define QCA956X_PLL_DDR_CONFIG1_REG			0x0c
#define QCA956X_PLL_CLK_CTRL_REG			0x10
#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG		0x28
#define QCA956X_PLL_ETH_XMII_CONTROL_REG		0x30
#define QCA956X_PLL_ETH_SGMII_SERDES_REG		0x4c

#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT		12
#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK		0x1f
#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT		19
#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK		0x7

#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT		0
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK		0x1f
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT		5
#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK		0x1fff
#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT		18
#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK		0x1ff

#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT		16
#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK		0x1f
#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT		23
#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK		0x7

#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT		0
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK		0x1f
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT		5
#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK		0x1fff
#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT		18
#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK		0x1ff

#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS		BIT(2)
#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS		BIT(3)
#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS		BIT(4)
#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT		5
#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK		0x1f
#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT		10
#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK		0x1f
#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT		15
#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK		0x1f
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL	BIT(20)
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL	BIT(21)
#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL		BIT(24)

#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB		BIT(5)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1		BIT(6)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL		BIT(7)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK	 0xf
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP		BIT(12)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2		BIT(13)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1		BIT(14)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2		BIT(15)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE	BIT(16)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE		BIT(17)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL		BIT(18)
#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL		BIT(19)

#define QCA956X_PLL_ETH_XMII_TX_INVERT			BIT(1)
#define QCA956X_PLL_ETH_XMII_GIGE			BIT(25)
#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT		28
#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK		0x3
#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT		26
#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK		3

#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT		BIT(2)
#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK			BIT(1)
#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL			BIT(0)

/*
 * USB_CONFIG block
 */
#define AR71XX_USB_CTRL_REG_FLADJ	0x00
#define AR71XX_USB_CTRL_REG_CONFIG	0x04

/*
 * RESET block
 */
#define AR71XX_RESET_REG_TIMER			0x00
#define AR71XX_RESET_REG_TIMER_RELOAD		0x04
#define AR71XX_RESET_REG_WDOG_CTRL		0x08
#define AR71XX_RESET_REG_WDOG			0x0c
#define AR71XX_RESET_REG_MISC_INT_STATUS	0x10
#define AR71XX_RESET_REG_MISC_INT_ENABLE	0x14
#define AR71XX_RESET_REG_PCI_INT_STATUS		0x18
#define AR71XX_RESET_REG_PCI_INT_ENABLE		0x1c
#define AR71XX_RESET_REG_GLOBAL_INT_STATUS	0x20
#define AR71XX_RESET_REG_RESET_MODULE		0x24
#define AR71XX_RESET_REG_PERFC_CTRL		0x2c
#define AR71XX_RESET_REG_PERFC0			0x30
#define AR71XX_RESET_REG_PERFC1			0x34
#define AR71XX_RESET_REG_REV_ID			0x90

#define AR913X_RESET_REG_GLOBAL_INT_STATUS	0x18
#define AR913X_RESET_REG_RESET_MODULE		0x1c
#define AR913X_RESET_REG_PERF_CTRL		0x20
#define AR913X_RESET_REG_PERFC0			0x24
#define AR913X_RESET_REG_PERFC1			0x28

#define AR724X_RESET_REG_RESET_MODULE		0x1c

#define AR933X_RESET_REG_RESET_MODULE		0x1c
#define AR933X_RESET_REG_BOOTSTRAP		0xac

#define AR934X_RESET_REG_RESET_MODULE		0x1c
#define AR934X_RESET_REG_BOOTSTRAP		0xb0
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac

#define QCA953X_RESET_REG_RESET_MODULE		0x1c
#define QCA953X_RESET_REG_BOOTSTRAP		0xb0
#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac

#define QCA955X_RESET_REG_RESET_MODULE		0x1c
#define QCA955X_RESET_REG_BOOTSTRAP		0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS	0xac

#define QCA956X_RESET_REG_RESET_MODULE		0x1c
#define QCA956X_RESET_REG_BOOTSTRAP		0xb0
#define QCA956X_RESET_REG_EXT_INT_STATUS	0xac

#define MISC_INT_MIPS_SI_TIMERINT_MASK	BIT(28)
#define MISC_INT_ETHSW			BIT(12)
#define MISC_INT_TIMER4			BIT(10)
#define MISC_INT_TIMER3			BIT(9)
#define MISC_INT_TIMER2			BIT(8)
#define MISC_INT_DMA			BIT(7)
#define MISC_INT_OHCI			BIT(6)
#define MISC_INT_PERFC			BIT(5)
#define MISC_INT_WDOG			BIT(4)
#define MISC_INT_UART			BIT(3)
#define MISC_INT_GPIO			BIT(2)
#define MISC_INT_ERROR			BIT(1)
#define MISC_INT_TIMER			BIT(0)

#define AR71XX_RESET_EXTERNAL		BIT(28)
#define AR71XX_RESET_FULL_CHIP		BIT(24)
#define AR71XX_RESET_CPU_NMI		BIT(21)
#define AR71XX_RESET_CPU_COLD		BIT(20)
#define AR71XX_RESET_DMA		BIT(19)
#define AR71XX_RESET_SLIC		BIT(18)
#define AR71XX_RESET_STEREO		BIT(17)
#define AR71XX_RESET_DDR		BIT(16)
#define AR71XX_RESET_GE1_MAC		BIT(13)
#define AR71XX_RESET_GE1_PHY		BIT(12)
#define AR71XX_RESET_USBSUS_OVERRIDE	BIT(10)
#define AR71XX_RESET_GE0_MAC		BIT(9)
#define AR71XX_RESET_GE0_PHY		BIT(8)
#define AR71XX_RESET_USB_OHCI_DLL	BIT(6)
#define AR71XX_RESET_USB_HOST		BIT(5)
#define AR71XX_RESET_USB_PHY		BIT(4)
#define AR71XX_RESET_PCI_BUS		BIT(1)
#define AR71XX_RESET_PCI_CORE		BIT(0)

#define AR7240_RESET_USB_HOST		BIT(5)
#define AR7240_RESET_OHCI_DLL		BIT(3)

#define AR724X_RESET_GE1_MDIO		BIT(23)
#define AR724X_RESET_GE0_MDIO		BIT(22)
#define AR724X_RESET_PCIE_PHY_SERIAL	BIT(10)
#define AR724X_RESET_PCIE_PHY		BIT(7)
#define AR724X_RESET_PCIE		BIT(6)
#define AR724X_RESET_USB_HOST		BIT(5)
#define AR724X_RESET_USB_PHY		BIT(4)
#define AR724X_RESET_USBSUS_OVERRIDE	BIT(3)

#define AR913X_RESET_AMBA2WMAC		BIT(22)
#define AR913X_RESET_USBSUS_OVERRIDE	BIT(10)
#define AR913X_RESET_USB_HOST		BIT(5)
#define AR913X_RESET_USB_PHY		BIT(4)

#define AR933X_RESET_GE1_MDIO		BIT(23)
#define AR933X_RESET_GE0_MDIO		BIT(22)
#define AR933X_RESET_GE1_MAC		BIT(13)
#define AR933X_RESET_WMAC		BIT(11)
#define AR933X_RESET_GE0_MAC		BIT(9)
#define AR933X_RESET_USB_HOST		BIT(5)
#define AR933X_RESET_USB_PHY		BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE	BIT(3)

#define AR934X_RESET_HOST		BIT(31)
#define AR934X_RESET_SLIC		BIT(30)
#define AR934X_RESET_HDMA		BIT(29)
#define AR934X_RESET_EXTERNAL		BIT(28)
#define AR934X_RESET_RTC		BIT(27)
#define AR934X_RESET_PCIE_EP_INT	BIT(26)
#define AR934X_RESET_CHKSUM_ACC		BIT(25)
#define AR934X_RESET_FULL_CHIP		BIT(24)
#define AR934X_RESET_GE1_MDIO		BIT(23)
#define AR934X_RESET_GE0_MDIO		BIT(22)
#define AR934X_RESET_CPU_NMI		BIT(21)
#define AR934X_RESET_CPU_COLD		BIT(20)
#define AR934X_RESET_HOST_RESET_INT	BIT(19)
#define AR934X_RESET_PCIE_EP		BIT(18)
#define AR934X_RESET_UART1		BIT(17)
#define AR934X_RESET_DDR		BIT(16)
#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
#define AR934X_RESET_NANDF		BIT(14)
#define AR934X_RESET_GE1_MAC		BIT(13)
#define AR934X_RESET_ETH_SWITCH_ANALOG	BIT(12)
#define AR934X_RESET_USB_PHY_ANALOG	BIT(11)
#define AR934X_RESET_HOST_DMA_INT	BIT(10)
#define AR934X_RESET_GE0_MAC		BIT(9)
#define AR934X_RESET_ETH_SWITCH		BIT(8)
#define AR934X_RESET_PCIE_PHY		BIT(7)
#define AR934X_RESET_PCIE		BIT(6)
#define AR934X_RESET_USB_HOST		BIT(5)
#define AR934X_RESET_USB_PHY		BIT(4)
#define AR934X_RESET_USBSUS_OVERRIDE	BIT(3)
#define AR934X_RESET_LUT		BIT(2)
#define AR934X_RESET_MBOX		BIT(1)
#define AR934X_RESET_I2S		BIT(0)

#define QCA953X_RESET_USB_EXT_PWR	BIT(29)
#define QCA953X_RESET_EXTERNAL		BIT(28)
#define QCA953X_RESET_RTC		BIT(27)
#define QCA953X_RESET_FULL_CHIP		BIT(24)
#define QCA953X_RESET_GE1_MDIO		BIT(23)
#define QCA953X_RESET_GE0_MDIO		BIT(22)
#define QCA953X_RESET_CPU_NMI		BIT(21)
#define QCA953X_RESET_CPU_COLD		BIT(20)
#define QCA953X_RESET_DDR		BIT(16)
#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
#define QCA953X_RESET_GE1_MAC		BIT(13)
#define QCA953X_RESET_ETH_SWITCH_ANALOG	BIT(12)
#define QCA953X_RESET_USB_PHY_ANALOG	BIT(11)
#define QCA953X_RESET_GE0_MAC		BIT(9)
#define QCA953X_RESET_ETH_SWITCH	BIT(8)
#define QCA953X_RESET_PCIE_PHY		BIT(7)
#define QCA953X_RESET_PCIE		BIT(6)
#define QCA953X_RESET_USB_HOST		BIT(5)
#define QCA953X_RESET_USB_PHY		BIT(4)
#define QCA953X_RESET_USBSUS_OVERRIDE	BIT(3)

#define QCA955X_RESET_HOST		BIT(31)
#define QCA955X_RESET_SLIC		BIT(30)
#define QCA955X_RESET_HDMA		BIT(29)
#define QCA955X_RESET_EXTERNAL		BIT(28)
#define QCA955X_RESET_RTC		BIT(27)
#define QCA955X_RESET_PCIE_EP_INT	BIT(26)
#define QCA955X_RESET_CHKSUM_ACC	BIT(25)
#define QCA955X_RESET_FULL_CHIP		BIT(24)
#define QCA955X_RESET_GE1_MDIO		BIT(23)
#define QCA955X_RESET_GE0_MDIO		BIT(22)
#define QCA955X_RESET_CPU_NMI		BIT(21)
#define QCA955X_RESET_CPU_COLD		BIT(20)
#define QCA955X_RESET_HOST_RESET_INT	BIT(19)
#define QCA955X_RESET_PCIE_EP		BIT(18)
#define QCA955X_RESET_UART1		BIT(17)
#define QCA955X_RESET_DDR		BIT(16)
#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
#define QCA955X_RESET_NANDF		BIT(14)
#define QCA955X_RESET_GE1_MAC		BIT(13)
#define QCA955X_RESET_SGMII_ANALOG	BIT(12)
#define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
#define QCA955X_RESET_HOST_DMA_INT	BIT(10)
#define QCA955X_RESET_GE0_MAC		BIT(9)
#define QCA955X_RESET_SGMII		BIT(8)
#define QCA955X_RESET_PCIE_PHY		BIT(7)
#define QCA955X_RESET_PCIE		BIT(6)
#define QCA955X_RESET_USB_HOST		BIT(5)
#define QCA955X_RESET_USB_PHY		BIT(4)
#define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
#define QCA955X_RESET_LUT		BIT(2)
#define QCA955X_RESET_MBOX		BIT(1)
#define QCA955X_RESET_I2S		BIT(0)

#define QCA956X_RESET_EXTERNAL		BIT(28)
#define QCA956X_RESET_FULL_CHIP		BIT(24)
#define QCA956X_RESET_GE1_MDIO		BIT(23)
#define QCA956X_RESET_GE0_MDIO		BIT(22)
#define QCA956X_RESET_CPU_NMI		BIT(21)
#define QCA956X_RESET_CPU_COLD		BIT(20)
#define QCA956X_RESET_DMA		BIT(19)
#define QCA956X_RESET_DDR		BIT(16)
#define QCA956X_RESET_GE1_MAC		BIT(13)
#define QCA956X_RESET_SGMII_ANALOG	BIT(12)
#define QCA956X_RESET_USB_PHY_ANALOG	BIT(11)
#define QCA956X_RESET_GE0_MAC		BIT(9)
#define QCA956X_RESET_SGMII		BIT(8)
#define QCA956X_RESET_USB_HOST		BIT(5)
#define QCA956X_RESET_USB_PHY		BIT(4)
#define QCA956X_RESET_USBSUS_OVERRIDE	BIT(3)
#define QCA956X_RESET_SWITCH_ANALOG	BIT(2)
#define QCA956X_RESET_SWITCH		BIT(0)

#define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
#define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)

#define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
#define AR934X_BOOTSTRAP_SW_OPTION7	BIT(22)
#define AR934X_BOOTSTRAP_SW_OPTION6	BIT(21)
#define AR934X_BOOTSTRAP_SW_OPTION5	BIT(20)
#define AR934X_BOOTSTRAP_SW_OPTION4	BIT(19)
#define AR934X_BOOTSTRAP_SW_OPTION3	BIT(18)
#define AR934X_BOOTSTRAP_SW_OPTION2	BIT(17)
#define AR934X_BOOTSTRAP_SW_OPTION1	BIT(16)
#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
#define AR934X_BOOTSTRAP_PCIE_RC	BIT(6)
#define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
#define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
#define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define AR934X_BOOTSTRAP_DDR1		BIT(0)

#define QCA953X_BOOTSTRAP_SW_OPTION2	BIT(12)
#define QCA953X_BOOTSTRAP_SW_OPTION1	BIT(11)
#define QCA953X_BOOTSTRAP_EJTAG_MODE	BIT(5)
#define QCA953X_BOOTSTRAP_REF_CLK_40	BIT(4)
#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define QCA953X_BOOTSTRAP_DDR1		BIT(0)

#define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)

#define QCA956X_BOOTSTRAP_REF_CLK_40	BIT(2)

#define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
#define AR934X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
#define AR934X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
#define AR934X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
#define AR934X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
#define AR934X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
#define AR934X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)

#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
	 AR934X_PCIE_WMAC_INT_PCIE_RC3)

#define QCA953X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
#define QCA953X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
#define QCA953X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
	(QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
	 QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)

#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
	(QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
	 QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
	 QCA953X_PCIE_WMAC_INT_PCIE_RC3)

#define QCA955X_EXT_INT_WMAC_MISC		BIT(0)
#define QCA955X_EXT_INT_WMAC_TX			BIT(1)
#define QCA955X_EXT_INT_WMAC_RXLP		BIT(2)
#define QCA955X_EXT_INT_WMAC_RXHP		BIT(3)
#define QCA955X_EXT_INT_PCIE_RC1		BIT(4)
#define QCA955X_EXT_INT_PCIE_RC1_INT0		BIT(5)
#define QCA955X_EXT_INT_PCIE_RC1_INT1		BIT(6)
#define QCA955X_EXT_INT_PCIE_RC1_INT2		BIT(7)
#define QCA955X_EXT_INT_PCIE_RC1_INT3		BIT(8)
#define QCA955X_EXT_INT_PCIE_RC2		BIT(12)
#define QCA955X_EXT_INT_PCIE_RC2_INT0		BIT(13)
#define QCA955X_EXT_INT_PCIE_RC2_INT1		BIT(14)
#define QCA955X_EXT_INT_PCIE_RC2_INT2		BIT(15)
#define QCA955X_EXT_INT_PCIE_RC2_INT3		BIT(16)
#define QCA955X_EXT_INT_USB1			BIT(24)
#define QCA955X_EXT_INT_USB2			BIT(28)

#define QCA955X_EXT_INT_WMAC_ALL \
	(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
	 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)

#define QCA955X_EXT_INT_PCIE_RC1_ALL \
	(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
	 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
	 QCA955X_EXT_INT_PCIE_RC1_INT3)

#define QCA955X_EXT_INT_PCIE_RC2_ALL \
	(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
	 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
	 QCA955X_EXT_INT_PCIE_RC2_INT3)

#define QCA956X_EXT_INT_WMAC_MISC		BIT(0)
#define QCA956X_EXT_INT_WMAC_TX			BIT(1)
#define QCA956X_EXT_INT_WMAC_RXLP		BIT(2)
#define QCA956X_EXT_INT_WMAC_RXHP		BIT(3)
#define QCA956X_EXT_INT_PCIE_RC1		BIT(4)
#define QCA956X_EXT_INT_PCIE_RC1_INT0		BIT(5)
#define QCA956X_EXT_INT_PCIE_RC1_INT1		BIT(6)
#define QCA956X_EXT_INT_PCIE_RC1_INT2		BIT(7)
#define QCA956X_EXT_INT_PCIE_RC1_INT3		BIT(8)
#define QCA956X_EXT_INT_PCIE_RC2		BIT(12)
#define QCA956X_EXT_INT_PCIE_RC2_INT0		BIT(13)
#define QCA956X_EXT_INT_PCIE_RC2_INT1		BIT(14)
#define QCA956X_EXT_INT_PCIE_RC2_INT2		BIT(15)
#define QCA956X_EXT_INT_PCIE_RC2_INT3		BIT(16)
#define QCA956X_EXT_INT_USB1			BIT(24)
#define QCA956X_EXT_INT_USB2			BIT(28)

#define QCA956X_EXT_INT_WMAC_ALL \
	(QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
	 QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)

#define QCA956X_EXT_INT_PCIE_RC1_ALL \
	(QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
	 QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
	 QCA956X_EXT_INT_PCIE_RC1_INT3)

#define QCA956X_EXT_INT_PCIE_RC2_ALL \
	(QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
	 QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
	 QCA956X_EXT_INT_PCIE_RC2_INT3)

#define REV_ID_MAJOR_MASK		0xfff0
#define REV_ID_MAJOR_AR71XX		0x00a0
#define REV_ID_MAJOR_AR913X		0x00b0
#define REV_ID_MAJOR_AR7240		0x00c0
#define REV_ID_MAJOR_AR7241		0x0100
#define REV_ID_MAJOR_AR7242		0x1100
#define REV_ID_MAJOR_AR9330		0x0110
#define REV_ID_MAJOR_AR9331		0x1110
#define REV_ID_MAJOR_AR9341		0x0120
#define REV_ID_MAJOR_AR9342		0x1120
#define REV_ID_MAJOR_AR9344		0x2120
#define REV_ID_MAJOR_QCA9533		0x0140
#define REV_ID_MAJOR_QCA9533_V2		0x0160
#define REV_ID_MAJOR_QCA9556		0x0130
#define REV_ID_MAJOR_QCA9558		0x1130
#define REV_ID_MAJOR_TP9343		0x0150
#define REV_ID_MAJOR_QCA956X		0x1150

#define AR71XX_REV_ID_MINOR_MASK	0x3
#define AR71XX_REV_ID_MINOR_AR7130	0x0
#define AR71XX_REV_ID_MINOR_AR7141	0x1
#define AR71XX_REV_ID_MINOR_AR7161	0x2
#define AR71XX_REV_ID_REVISION_MASK	0x3
#define AR71XX_REV_ID_REVISION_SHIFT	2

#define AR913X_REV_ID_MINOR_MASK	0x3
#define AR913X_REV_ID_MINOR_AR9130	0x0
#define AR913X_REV_ID_MINOR_AR9132	0x1
#define AR913X_REV_ID_REVISION_MASK	0x3
#define AR913X_REV_ID_REVISION_SHIFT	2

#define AR933X_REV_ID_REVISION_MASK	0x3

#define AR724X_REV_ID_REVISION_MASK	0x3

#define AR934X_REV_ID_REVISION_MASK	0xf

#define QCA953X_REV_ID_REVISION_MASK	0xf

#define QCA955X_REV_ID_REVISION_MASK	0xf

#define QCA956X_REV_ID_REVISION_MASK	0xf

/*
 * SPI block
 */
#define AR71XX_SPI_REG_FS	0x00	/* Function Select */
#define AR71XX_SPI_REG_CTRL	0x04	/* SPI Control */
#define AR71XX_SPI_REG_IOC	0x08	/* SPI I/O Control */
#define AR71XX_SPI_REG_RDS	0x0c	/* Read Data Shift */

#define AR71XX_SPI_FS_GPIO	BIT(0)	/* Enable GPIO mode */

#define AR71XX_SPI_CTRL_RD	BIT(6)	/* Remap Disable */
#define AR71XX_SPI_CTRL_DIV_MASK 0x3f

#define AR71XX_SPI_IOC_DO	BIT(0)	/* Data Out pin */
#define AR71XX_SPI_IOC_CLK	BIT(8)	/* CLK pin */
#define AR71XX_SPI_IOC_CS(n)	BIT(16 + (n))
#define AR71XX_SPI_IOC_CS0	AR71XX_SPI_IOC_CS(0)
#define AR71XX_SPI_IOC_CS1	AR71XX_SPI_IOC_CS(1)
#define AR71XX_SPI_IOC_CS2	AR71XX_SPI_IOC_CS(2)
#define AR71XX_SPI_IOC_CS_ALL	(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
				 AR71XX_SPI_IOC_CS2)

/*
 * GPIO block
 */
#define AR71XX_GPIO_REG_OE		0x00
#define AR71XX_GPIO_REG_IN		0x04
#define AR71XX_GPIO_REG_OUT		0x08
#define AR71XX_GPIO_REG_SET		0x0c
#define AR71XX_GPIO_REG_CLEAR		0x10
#define AR71XX_GPIO_REG_INT_MODE	0x14
#define AR71XX_GPIO_REG_INT_TYPE	0x18
#define AR71XX_GPIO_REG_INT_POLARITY	0x1c
#define AR71XX_GPIO_REG_INT_PENDING	0x20
#define AR71XX_GPIO_REG_INT_ENABLE	0x24
#define AR71XX_GPIO_REG_FUNC		0x28

#define AR934X_GPIO_REG_OUT_FUNC0	0x2c
#define AR934X_GPIO_REG_OUT_FUNC1	0x30
#define AR934X_GPIO_REG_OUT_FUNC2	0x34
#define AR934X_GPIO_REG_OUT_FUNC3	0x38
#define AR934X_GPIO_REG_OUT_FUNC4	0x3c
#define AR934X_GPIO_REG_OUT_FUNC5	0x40
#define AR934X_GPIO_REG_FUNC		0x6c

#define QCA953X_GPIO_REG_OUT_FUNC0	0x2c
#define QCA953X_GPIO_REG_OUT_FUNC1	0x30
#define QCA953X_GPIO_REG_OUT_FUNC2	0x34
#define QCA953X_GPIO_REG_OUT_FUNC3	0x38
#define QCA953X_GPIO_REG_OUT_FUNC4	0x3c
#define QCA953X_GPIO_REG_IN_ENABLE0	0x44
#define QCA953X_GPIO_REG_FUNC		0x6c

#define QCA953X_GPIO_OUT_MUX_SPI_CS1		10
#define QCA953X_GPIO_OUT_MUX_SPI_CS2		11
#define QCA953X_GPIO_OUT_MUX_SPI_CS0		9
#define QCA953X_GPIO_OUT_MUX_SPI_CLK		8
#define QCA953X_GPIO_OUT_MUX_SPI_MOSI		12
#define QCA953X_GPIO_OUT_MUX_LED_LINK1		41
#define QCA953X_GPIO_OUT_MUX_LED_LINK2		42
#define QCA953X_GPIO_OUT_MUX_LED_LINK3		43
#define QCA953X_GPIO_OUT_MUX_LED_LINK4		44
#define QCA953X_GPIO_OUT_MUX_LED_LINK5		45

#define QCA955X_GPIO_REG_OUT_FUNC0	0x2c
#define QCA955X_GPIO_REG_OUT_FUNC1	0x30
#define QCA955X_GPIO_REG_OUT_FUNC2	0x34
#define QCA955X_GPIO_REG_OUT_FUNC3	0x38
#define QCA955X_GPIO_REG_OUT_FUNC4	0x3c
#define QCA955X_GPIO_REG_OUT_FUNC5	0x40
#define QCA955X_GPIO_REG_FUNC		0x6c

#define QCA956X_GPIO_REG_OUT_FUNC0	0x2c
#define QCA956X_GPIO_REG_OUT_FUNC1	0x30
#define QCA956X_GPIO_REG_OUT_FUNC2	0x34
#define QCA956X_GPIO_REG_OUT_FUNC3	0x38
#define QCA956X_GPIO_REG_OUT_FUNC4	0x3c
#define QCA956X_GPIO_REG_OUT_FUNC5	0x40
#define QCA956X_GPIO_REG_IN_ENABLE0	0x44
#define QCA956X_GPIO_REG_IN_ENABLE3	0x50
#define QCA956X_GPIO_REG_FUNC		0x6c

#define QCA956X_GPIO_OUT_MUX_GE0_MDO	32
#define QCA956X_GPIO_OUT_MUX_GE0_MDC	33

#define AR71XX_GPIO_COUNT		16
#define AR7240_GPIO_COUNT		18
#define AR7241_GPIO_COUNT		20
#define AR913X_GPIO_COUNT		22
#define AR933X_GPIO_COUNT		30
#define AR934X_GPIO_COUNT		23
#define QCA953X_GPIO_COUNT		18
#define QCA955X_GPIO_COUNT		24
#define QCA956X_GPIO_COUNT		23

/*
 * SRIF block
 */
#define AR934X_SRIF_CPU_DPLL1_REG	0x1c0
#define AR934X_SRIF_CPU_DPLL2_REG	0x1c4
#define AR934X_SRIF_CPU_DPLL3_REG	0x1c8

#define AR934X_SRIF_DDR_DPLL1_REG	0x240
#define AR934X_SRIF_DDR_DPLL2_REG	0x244
#define AR934X_SRIF_DDR_DPLL3_REG	0x248

#define AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
#define AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
#define AR934X_SRIF_DPLL1_NINT_SHIFT	18
#define AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
#define AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff

#define AR934X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7

#define QCA953X_SRIF_CPU_DPLL1_REG	0x1c0
#define QCA953X_SRIF_CPU_DPLL2_REG	0x1c4
#define QCA953X_SRIF_CPU_DPLL3_REG	0x1c8

#define QCA953X_SRIF_DDR_DPLL1_REG	0x240
#define QCA953X_SRIF_DDR_DPLL2_REG	0x244
#define QCA953X_SRIF_DDR_DPLL3_REG	0x248

#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT	27
#define QCA953X_SRIF_DPLL1_REFDIV_MASK	0x1f
#define QCA953X_SRIF_DPLL1_NINT_SHIFT	18
#define QCA953X_SRIF_DPLL1_NINT_MASK	0x1ff
#define QCA953X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff

#define QCA953X_SRIF_DPLL2_LOCAL_PLL	BIT(30)
#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT	13
#define QCA953X_SRIF_DPLL2_OUTDIV_MASK	0x7

#define AR71XX_GPIO_FUNC_STEREO_EN		BIT(17)
#define AR71XX_GPIO_FUNC_SLIC_EN		BIT(16)
#define AR71XX_GPIO_FUNC_SPI_CS2_EN		BIT(13)
#define AR71XX_GPIO_FUNC_SPI_CS1_EN		BIT(12)
#define AR71XX_GPIO_FUNC_UART_EN		BIT(8)
#define AR71XX_GPIO_FUNC_USB_OC_EN		BIT(4)
#define AR71XX_GPIO_FUNC_USB_CLK_EN		BIT(0)

#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN		BIT(19)
#define AR724X_GPIO_FUNC_SPI_EN			BIT(18)
#define AR724X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
#define AR724X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
#define AR724X_GPIO_FUNC_CLK_OBS5_EN		BIT(12)
#define AR724X_GPIO_FUNC_CLK_OBS4_EN		BIT(11)
#define AR724X_GPIO_FUNC_CLK_OBS3_EN		BIT(10)
#define AR724X_GPIO_FUNC_CLK_OBS2_EN		BIT(9)
#define AR724X_GPIO_FUNC_CLK_OBS1_EN		BIT(8)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
#define AR724X_GPIO_FUNC_UART_EN		BIT(1)
#define AR724X_GPIO_FUNC_JTAG_DISABLE		BIT(0)

#define AR913X_GPIO_FUNC_WMAC_LED_EN		BIT(22)
#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN		BIT(21)
#define AR913X_GPIO_FUNC_I2S_REFCLKEN		BIT(20)
#define AR913X_GPIO_FUNC_I2S_MCKEN		BIT(19)
#define AR913X_GPIO_FUNC_I2S1_EN		BIT(18)
#define AR913X_GPIO_FUNC_I2S0_EN		BIT(17)
#define AR913X_GPIO_FUNC_SLIC_EN		BIT(16)
#define AR913X_GPIO_FUNC_UART_RTSCTS_EN		BIT(9)
#define AR913X_GPIO_FUNC_UART_EN		BIT(8)
#define AR913X_GPIO_FUNC_USB_CLK_EN		BIT(4)

#define AR933X_GPIO_FUNC_SPDIF2TCK		BIT(31)
#define AR933X_GPIO_FUNC_SPDIF_EN		BIT(30)
#define AR933X_GPIO_FUNC_I2SO_22_18_EN		BIT(29)
#define AR933X_GPIO_FUNC_I2S_MCK_EN		BIT(27)
#define AR933X_GPIO_FUNC_I2SO_EN		BIT(26)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL	BIT(25)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL	BIT(24)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT	BIT(23)
#define AR933X_GPIO_FUNC_SPI_EN			BIT(18)
#define AR933X_GPIO_FUNC_SPI_CS_EN2		BIT(14)
#define AR933X_GPIO_FUNC_SPI_CS_EN1		BIT(13)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN	BIT(7)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN	BIT(6)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN	BIT(5)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN	BIT(4)
#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN	BIT(3)
#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN	BIT(2)
#define AR933X_GPIO_FUNC_UART_EN		BIT(1)
#define AR933X_GPIO_FUNC_JTAG_DISABLE		BIT(0)

#define AR934X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
#define AR934X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
#define AR934X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
#define AR934X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
#define AR934X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
#define AR934X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
#define AR934X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
#define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
#define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)

#define AR934X_GPIO_OUT_GPIO		0
#define AR934X_GPIO_OUT_SPI_CS1	7
#define AR934X_GPIO_OUT_LED_LINK0	41
#define AR934X_GPIO_OUT_LED_LINK1	42
#define AR934X_GPIO_OUT_LED_LINK2	43
#define AR934X_GPIO_OUT_LED_LINK3	44
#define AR934X_GPIO_OUT_LED_LINK4	45
#define AR934X_GPIO_OUT_EXT_LNA0	46
#define AR934X_GPIO_OUT_EXT_LNA1	47

#define QCA955X_GPIO_FUNC_CLK_OBS7_EN		BIT(9)
#define QCA955X_GPIO_FUNC_CLK_OBS6_EN		BIT(8)
#define QCA955X_GPIO_FUNC_CLK_OBS5_EN		BIT(7)
#define QCA955X_GPIO_FUNC_CLK_OBS4_EN		BIT(6)
#define QCA955X_GPIO_FUNC_CLK_OBS3_EN		BIT(5)
#define QCA955X_GPIO_FUNC_CLK_OBS2_EN		BIT(4)
#define QCA955X_GPIO_FUNC_CLK_OBS1_EN		BIT(3)
#define QCA955X_GPIO_FUNC_JTAG_DISABLE		BIT(1)

#define QCA955X_GPIO_OUT_GPIO		0
#define QCA955X_MII_EXT_MDI		1
#define QCA955X_SLIC_DATA_OUT		3
#define QCA955X_SLIC_PCM_FS		4
#define QCA955X_SLIC_PCM_CLK		5
#define QCA955X_SPI_CLK			8
#define QCA955X_SPI_CS_0		9
#define QCA955X_SPI_CS_1		10
#define QCA955X_SPI_CS_2		11
#define QCA955X_SPI_MISO		12
#define QCA955X_I2S_CLK			13
#define QCA955X_I2S_WS			14
#define QCA955X_I2S_SD			15
#define QCA955X_I2S_MCK			16
#define QCA955X_SPDIF_OUT		17
#define QCA955X_UART1_TD		18
#define QCA955X_UART1_RTS		19
#define QCA955X_UART1_RD		20
#define QCA955X_UART1_CTS		21
#define QCA955X_UART0_SOUT		22
#define QCA955X_SPDIF2_OUT		23
#define QCA955X_LED_SGMII_SPEED0	24
#define QCA955X_LED_SGMII_SPEED1	25
#define QCA955X_LED_SGMII_DUPLEX	26
#define QCA955X_LED_SGMII_LINK_UP	27
#define QCA955X_SGMII_SPEED0_INVERT	28
#define QCA955X_SGMII_SPEED1_INVERT	29
#define QCA955X_SGMII_DUPLEX_INVERT	30
#define QCA955X_SGMII_LINK_UP_INVERT	31
#define QCA955X_GE1_MII_MDO		32
#define QCA955X_GE1_MII_MDC		33
#define QCA955X_SWCOM2			38
#define QCA955X_SWCOM3			39
#define QCA955X_MAC2_GPIO		40
#define QCA955X_MAC3_GPIO		41
#define QCA955X_ATT_LED			42
#define QCA955X_PWR_LED			43
#define QCA955X_TX_FRAME		44
#define QCA955X_RX_CLEAR_EXTERNAL	45
#define QCA955X_LED_NETWORK_EN		46
#define QCA955X_LED_POWER_EN		47
#define QCA955X_WMAC_GLUE_WOW		68
#define QCA955X_RX_CLEAR_EXTENSION	70
#define QCA955X_CP_NAND_CS1		73
#define QCA955X_USB_SUSPEND		74
#define QCA955X_ETH_TX_ERR		75
#define QCA955X_DDR_DQ_OE		76
#define QCA955X_CLKREQ_N_EP		77
#define QCA955X_CLKREQ_N_RC		78
#define QCA955X_CLK_OBS0		79
#define QCA955X_CLK_OBS1		80
#define QCA955X_CLK_OBS2		81
#define QCA955X_CLK_OBS3		82
#define QCA955X_CLK_OBS4		83
#define QCA955X_CLK_OBS5		84

/*
 * MII_CTRL block
 */
#define AR71XX_MII_REG_MII0_CTRL	0x00
#define AR71XX_MII_REG_MII1_CTRL	0x04

#define AR71XX_MII_CTRL_IF_MASK		3
#define AR71XX_MII_CTRL_SPEED_SHIFT	4
#define AR71XX_MII_CTRL_SPEED_MASK	3
#define AR71XX_MII_CTRL_SPEED_10	0
#define AR71XX_MII_CTRL_SPEED_100	1
#define AR71XX_MII_CTRL_SPEED_1000	2

#define AR71XX_MII0_CTRL_IF_GMII	0
#define AR71XX_MII0_CTRL_IF_MII		1
#define AR71XX_MII0_CTRL_IF_RGMII	2
#define AR71XX_MII0_CTRL_IF_RMII	3

#define AR71XX_MII1_CTRL_IF_RGMII	0
#define AR71XX_MII1_CTRL_IF_RMII	1

/*
 * AR933X GMAC interface
 */
#define AR933X_GMAC_REG_ETH_CFG		0x00

#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
#define AR933X_ETH_CFG_MII_GE0		BIT(1)
#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)

/*
 * AR934X GMAC Interface
 */
#define AR934X_GMAC_REG_ETH_CFG		0x00

#define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
#define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
#define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
#define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
#define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
#define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
#define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
#define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
#define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
#define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
#define AR934X_ETH_CFG_RXD_DELAY_MASK   0x3
#define AR934X_ETH_CFG_RXD_DELAY_SHIFT  14
#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
#define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16

/*
 * QCA953X GMAC Interface
 */
#define QCA953X_GMAC_REG_ETH_CFG		0x00

#define QCA953X_ETH_CFG_SW_ONLY_MODE		BIT(6)
#define QCA953X_ETH_CFG_SW_PHY_SWAP		BIT(7)
#define QCA953X_ETH_CFG_SW_APB_ACCESS		BIT(9)
#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)

/*
 * QCA955X GMAC Interface
 */

#define QCA955X_GMAC_REG_ETH_CFG	0x00
#define QCA955X_GMAC_REG_SGMII_SERDES	0x18

#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
#define QCA955X_ETH_CFG_MII_GE0		BIT(1)
#define QCA955X_ETH_CFG_GMII_GE0	BIT(2)
#define QCA955X_ETH_CFG_MII_GE0_MASTER	BIT(3)
#define QCA955X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
#define QCA955X_ETH_CFG_GE0_ERR_EN	BIT(5)
#define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
#define QCA955X_ETH_CFG_RMII_GE0	BIT(10)
#define QCA955X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
#define QCA955X_ETH_CFG_RMII_GE0_MASTER	BIT(12)
#define QCA955X_ETH_CFG_RXD_DELAY_MASK	0x3
#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT	14
#define QCA955X_ETH_CFG_RDV_DELAY	BIT(16)
#define QCA955X_ETH_CFG_RDV_DELAY_MASK	0x3
#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT	16
#define QCA955X_ETH_CFG_TXD_DELAY_MASK	0x3
#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT	18
#define QCA955X_ETH_CFG_TXE_DELAY_MASK	0x3
#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT	20

#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS	BIT(15)
#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
/*
 * QCA956X GMAC Interface
 */

#define QCA956X_GMAC_REG_ETH_CFG	0x00
#define QCA956X_GMAC_REG_SGMII_RESET	0x14
#define QCA956X_GMAC_REG_SGMII_SERDES	0x18
#define QCA956X_GMAC_REG_MR_AN_CONTROL	0x1c
#define QCA956X_GMAC_REG_SGMII_CONFIG	0x34
#define QCA956X_GMAC_REG_SGMII_DEBUG	0x58

#define QCA956X_ETH_CFG_RGMII_EN		BIT(0)
#define QCA956X_ETH_CFG_GE0_SGMII		BIT(6)
#define QCA956X_ETH_CFG_SW_ONLY_MODE		BIT(7)
#define QCA956X_ETH_CFG_SW_PHY_SWAP		BIT(8)
#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(9)
#define QCA956X_ETH_CFG_SW_APB_ACCESS		BIT(10)
#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
#define QCA956X_ETH_CFG_RXD_DELAY_MASK		0x3
#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT		14
#define QCA956X_ETH_CFG_RDV_DELAY_MASK		0x3
#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT		16

#define QCA956X_SGMII_RESET_RX_CLK_N_RESET	0x0
#define QCA956X_SGMII_RESET_RX_CLK_N		BIT(0)
#define QCA956X_SGMII_RESET_TX_CLK_N		BIT(1)
#define QCA956X_SGMII_RESET_RX_125M_N		BIT(2)
#define QCA956X_SGMII_RESET_TX_125M_N		BIT(3)
#define QCA956X_SGMII_RESET_HW_RX_125M_N	BIT(4)

#define QCA956X_SGMII_SERDES_CDR_BW_MASK	0x3
#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT	1
#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK	0x7
#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT	4
#define QCA956X_SGMII_SERDES_PLL_BW		BIT(8)
#define QCA956X_SGMII_SERDES_VCO_FAST		BIT(9)
#define QCA956X_SGMII_SERDES_VCO_SLOW		BIT(10)
#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS	BIT(15)
#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT	BIT(16)
#define QCA956X_SGMII_SERDES_FIBER_SDO		BIT(17)
#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT	27
#define QCA956X_SGMII_SERDES_VCO_REG_MASK	0xf

#define QCA956X_MR_AN_CONTROL_AN_ENABLE		BIT(12)
#define QCA956X_MR_AN_CONTROL_PHY_RESET		BIT(15)

#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT	0
#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK	0x7

#endif /* __ASM_MACH_AR71XX_REGS_H */

OHA YOOOO
����JFIF��� ( %!1!%)+...383-7(-.+  ---+--------------------+-----7------+-7-----+---++����"����M!1AQaq�"2���Rr��#3Bb�s����CSc��$4���D���TdE������'1!AQ"2q�a���� ?�Z�L�[�����=D�6]�T mѰx$�6��@ۣ`�Itl �"��(6�Dst�2:��Fk���x���4��K�h}�l �?r��@��!�Q��Y��?��-� =��O�����(6����<A�x%B��<A�x%B��<(6�@��.���*%���$e�m��T�wi��~H�]F�Ѱx"�`�Ul��ꃁ���RPl�6�UIA�x(���#�B��zy%�<�L���mvN �ԭ6�Y$Qk �S��䮰�K6ף�x�+�T��L4���>�C=j�������p�|J�ǥ���b=���Y�6g9��F1��Y�vݩ�`��塏��>� � �ݨ,�����A�o�=W*���"��>����� \ �"݄(꧈�y���9�m���d�aAD�u&�T��D �@$BITU�"��D�D!BH�� � �UTu� �^c�?�[ND�K�`�\F'�jf��<�G�G��B�q]�����!tl�6�]\4mѰx"��<�6��B�֊�o4.�Ah�8QM,�y�����%cLh��y�c����!�8Tb���h�!p�q�t����EIA�x'Pl �KT N h6�J�P7�6Ԩ�6恰&��� �� � ����R���)m�`8�nC�J���E��%H� D�"T �n��W�s+���x���+g�?t��@�����;�>�o��0�����|Ћ0�����|"�J�%EBBBB!X�����|��X��̟s��Ӭ��H獎ŏ m׷�0���—���2q����s�'q]�����7�%����hp8EAYy�Ӗc��9%�A� _g�ٙ���}ӯ�Ul�Ƽl Ѓ�a�ۮ9�i�*��R"�*������:��j�zE+�H ����kB�2�e��~��Zd# ��0Vr�T�ev������Y�����-8]o��x�~)�9��}W:RF֟��P�A�� ���G+hH�P6�����:���Ԁ��I�O{Y�F��$U"H�#2��*J����L��L�B�*��T`���(�-:�R�H Z��"�B�Ihh��B�B�����urP�%� ��9��7v",�!�A�b�X�V6F��� ���^K�+��f��qm^��'�9�K� �����o��! ��P�%B����E��}Xo�U��(BXJ󥯢t��u�&�}Xj +%�7+�c� �\��t�9t p*)��L�Z��T��KTC�NGT�PH pQ�� ɚ^qB ��8!�*��� P��"T iHS���n��W�s+���x���,mtG��@��D~���� } tY������Y���4����!!@!@!@!@�a�^h��R���*��|!���Us;����n:��#���4-h�chW꼝���%�+Z�kA��E%��4“M$�����@y�q˓��ʽ�� $U��������eH�-;�a�ކ�&����*IB� �Z�w��;c��|�3JZ@��-��w�k������Q�Ϊ �g�d���I��G����8�N�G�����(R)�2�_�]3;]z7]�2�w�r����I�Iĭ=15���b~ 2�{cuO�'෎V�nyI)��1s�� ����i�lT*�ݠ�������H��p��^j�C�Q�B*(������(m�Wb ���Z�)P*D$EGimZU�ViZ��┵\�P�L���IW���Eh����[榚V�R8+l��zV<�B�M�j�V�pw�%�*�UKYǒ}�J�% ���(�����HM��NQ�S�toԝ�ܪZd�ল���,UP�J�=�Z m�T��-]��y��*k+���:�%J��V���X�i�o6�D38�h�=� �'G�$�@��X��H�P�~��X��e�Ã�����4���WS��x�3���q�˓V�S��k'�K�w�N�w�eb��,��bcw�1�� �ȃ�%����͖��Bd�J��*V�Y��.;Kh�� �*���1 X���-�� �OJ��$ sCU��H�Zj���N��e�m�zT�"T��%���8�(Q�4 雐��d8���j�$NH�'$@�� �a�< ᴖ��K��W ��5}��{��-�����w�}�,Y����䴣�,��S�|�R��BT D!�R ^��I *I4m%Gk�2&�y�m$�k;�7m��sW���:�q��!汖s��]�i�;(��ƣ�7_�Ve�o\㛜K�y���T/.yܝ�2! �AB(BD��ꦽ� �EX�w2��\�����^{Nɥ�=����lB�V���y ��t||�K$�v��Ȃ>* D��Q��z$�y��F�MqD��(���鍵M2 �G� ;[r*4�T�Rd�oV#�t+���P�A-��v�*�>��PhU ���-QJ��Y�mE;k�"�F�?%���R��&������G�ӳhx;�i��h���5��+�Cr��8���B�:�+BI�Ϯ�LOٳ��=�~��,��b�t�C�6p\����x ��«�!{�ҽhh��7<� ĊW���<�CNw�ai�@��ںf����j#^�Ny���\^rRU9�1u`�RC% T)SCM��VtR��U溢�f���i�|��Y/SpWF�V ��*�A�5)%T9����'B��O "�TTTQZTm�Dv] �����U����������R�����5�/B^�.�/���"rE�8B)�"�P�D!Km�<W��y�� |�[�m���,Y\A�]��7��f����ѻ,H�Zj[���eh� (N+P�U"N�*���ء6L� 뛐�������"T D!BBT�"�#��I~%�͑�W ���Q���w��] ���.���.��<���O��Zl�,��S�|���%F��9"H�Cj�66��4Wy��NTR��i Y��� '����|���c<�fژ��E�����\>.�|hH�Yem��&��"h!!*lehjӼ �s�HQ�b���� pi�Η|h�'�Rh��SP3 ۽�$0��P X?�w�-;5���4h�{� ���/U�v ���ְ\2o��e�����@(��+�u���Ē�����B^��&�M]�B� �"��D��@!@!@!,�lΖF��W=���^����da�cehi�����_��#d��[ 9_=�]�Ù^�$!�-p8�u�(B�/� ��A�!�����\�F4q��3����:�[�>�w�ك�[���]��<��[�3�'��M+�yMH�R D�P��(�P��AJ�b Qq�F�bq�ߪ:J�$j��8�-5 ��z@�#��K� ڕ�N ԺKړ�^y߉�Ԭ.�tv��n9��w���n�|s�Z��;q"{���9�! �BJ��BMe��=�`���֍�&�Ba�{� ���v ���@�> ���lp�6������uRh�"�i�,ɯ�79o�*�� ��V�&�[\v��:�bq k�|���\͒��1��]q��C �xi")��*0w��{��0�c��������߸ɢj�X�MQ����Y�R%B�D�P��!�$@$J��J��K�����r^�V~�� p�KWg���.��m 뛶���L�Z Bã� U; �H7�V�A��+�B��r R7!�%\���!�!�!�� �a��W�����+��Z�cw���]�C�D��}˽��]��g���>KM���?���� G�4HI&����i=,�Ge��*��o���ׯ r�c�RZ����$� ����fӿ.:��q'\j�M\㼕j�g�߃rh�� � S\ ��g���d%UkY� ��?Nn>�Y$ &�,�[/I�ZC��>�a��S�K��p ��� �Ƭ�QY�X��h!M�m�h�8]p���y%� C/gt����ڭX��� c�iW\�;'�i�� �atd���ā�7(6L`��]�=��hP��.�ss��X�9�X��ji�;��t��\��V���0f�87�U�?k��ww3W�|��=L@� ���OG��bv�Z���uj��AD�BEjubӨ&����F�Wgb�G���:�uT1��ni���y|�X�Etu������n�k�D��q57���g�A�n ��X]&����+����sD%�0�p��<��Vtm�����Z���9�^�Y*�(�{�/��j���sn}uz�����_n����������MErjΎ��[#N-5�5�a\��cu]m��M�WN�b�_ p�t�q�~ '��H�- y�@7%Oj�h�y/B��d�k�-{o�,-5��i�4toWx꘳�_�(E�LJ�í�m;�]t��V�^23I�{�h�g�43-zJ�ֽ��g�Z "'!N��:� N������Qku�8�3�n^���s,�6(� �nv��.�),��eƷK�\K����IPO�A��������e�K���ڌ6����yW�)֋��Z}�m{쾙��x���{hyn+/EY�l�W!-�$�U.��I��� ��� �� �/M�;��Pݎx�"~+��Ή1�&ѯ���=����#�ыv�$�[�"�R��To�v~)�U�˨ x0^q��S���^�d����ʠ�W� ��5�B���dy"��&�õ���c��g�+��9��ugh�ޖG���7������ �곗Hz;f�L��`8���{"��؛f�1��&�)J[�I������!n��v��b�Ik{�������ŋ���qo�s\��}ɛ\*KO<=h�L�2�U��Z� ���v���[O��8�@7$t����4S2r�ʬm���)18op�?��]1%�<��&71�k�.�s$.?-��s�ïZ� C�DjFC�w֠r+�@U4U��xY2����N�w�S�\S+�� P�0D��� ����R�>*D�3�֎m�Fu��v^k��,�9�-�V����M�k���Rw֏�Z�[Y�=���q:Aů%�>�����O�0�pmӅC�^뇍6��+E��N�f>29^L����=e�gi�-0�����e�W5��U�E�x�і��(ZKH�F(�Y�mrA;Gf\�H�z�G��iw� �^�r�y������-.��9��2|�%���ÌR�����J��� x��ab��KD�꾏!�k��D�s4o���F/9�2��fv��?y���z;WLC�T�*���l�"�b[�qi��A� ����Vf�җ�W'fA������� ¢�#h?%.�҆�lߊ�_��w� 6�uA�*V�;M�y�*�OY����1MZ6��g1�PsWiv�e���%B����@�B"�@$�TQF�т@p�q֫9��+��F��bF� VljWx�B�%���L����ۗ$��˒r������ � � d�p:KZ����+��Z�c{��r��D�ކ}˿h}��"be�I !���-[��n�{ft�J`�ь7f#�\c�{rڱ����T0уQ~���Q��h�����9���;��Ֆr�Ts�Y�dt��L�ٳx�R�i�<�B�g�=��^caؤs�EI��SAEɤ6�\��b�pn_�Z�U�u�� c\}Z�a��y��B�PZ���'�Ya���Ʈ��N�� ��I�C��,Vp��+A^Y,��,h*��[P�!�|�����I-,nn��& �x��u )�T�o��%��]8-x�m�dh́�sz]�/�#�}�{� �uq*͚��1=��g27�4�l�;���Rn�v�G�zܑ`�Z9���j� �ᲈ�X̜�]�$���OYɊT��2� %BAJ����� �:�uԮU�j_� z'�48d�T'��F�g�rI�Ƹ��+ :��p� '$涨�䳶J5�k�48Tk�[;c��K=��zՕXʛuS��"��Q�8l �m��ˋ��k+���ᴇ��$V _�%$g��k��]��GZ�t�^ʹ�쮣��k��m�2V:9׊8c෎v%�8O�&}�����]�\�G4?��3F ,�6I9�k��^�����m���TЕm � J�P� ��}�� ��Y���2��}�&���{��|(Y�o���J���v�qܶ��EAA����BG�o<�Y1�K+�����۽���^�dŹ���-�v�����P��It���sh�VŦ���ޫ.H�4+�9m�ώ�Q �H���%D�@�!@�%@AFkK��B�&hCm��8'&7.A9y�P�$J�B�P�*BJp< �t���͑�W�����E- ��#�h�8��� {K�s���Zgu���m=IU�v���;!�cϴ� ��J�"r\ 0 p��+�8T��e]ĵy�rߧ\'�4s\�ep����� <�ޑ}ƶ!��9�V�Mk]R;1���4L���'2j���B��F@c���f���e=�k�t�n�?X��2W����j����&��Ꜩ�n�WԮ�5� �����G���|h�m�(ݹ��@Z��VY$?�6�qy$�'���l�z��Õ��I���pK_ny�Tlq��<��.#��)��&���0�)#;s�`k��xn5ʞ�4�-�Y� ���'�kFe���k%������=�{c9���u�L�Ut��,�`g���iS)Z��Z@���l8B��P1�y��Z�ѩ�\�㏲Vk���&K,��I4����iX!��U,���7‰l����`t��E�I��ʺN�P�(����k!�}֒�\q��-m'%؝CBh����aTn[�%Z}�C��0P>bs$�)�4���x��9E�&�^EQf��!�mt�z��8��ձhR�Rw�ͨ��{>g��(��c�C���p�� �޺ S��n� l���$lgn�ۂ����I�{݉$�XnM��-{��Z��E-����n��*Si/`s?%��8��6�<����� \7A��WZR#���Ǔi�˹ V2*��B�� �� T�=3n�&юA�� ���%��_O� ->���G�EgJ�C��a?��tl@����6��m��Q���p�s(^���*�� � �Tfi :�b��Ed���׀�|c���8^a���F�[J�~7*@n�3��2��j��mik^��NyF�J�g�������6���*@��Pg�珢�C�g��*=5���R��g�=U_��;G�~)&��M���\<�F,�]�&��<\o�L�]����g �� r޿��������$kk��i(�!�ݥE�V�E�;ͨ���헮�����5���TiTM�z��+N����Ī��J�e{ݺ6 �n$�q<�Y�!�1�yAs����.�@��U�%+�έ��u\]J�`�Mdփ��C���;3��:&�^��7NK ���øS��]��'�7v�M;�ä\BD�1�P:�J#i��u��e���mZ���<���X?eew'8��� �=��փ��.����Ԯe�c�e�O)�KZ9 rW,�����a#[���U[�03\ޚ�\QU�3���L<⵶Zv�dP2���4d5����\f���f�b���н�~��x��e�I��J��e�M2���d��oݴ���\|2M��6U�.��RYt|���O~�Q��pV���։c��C����E:�9��q@��N�D�;� �y�;M�Z�3���BԷڒ� ���Sm>�t��q�O@��=��s�6����H���EAi����e��;��ղ� p�<1T�&��79�ǽ�1#�5��'xµ��eODB��Z^;@7o5���"����xZ+�!S6�<�&�5��z���xa�.������73k�6��Yc@@ � ���D� ��� �f����438D75�/?��.�%����� � ?�7�L�)�u�����ٙ�S�]��s+���?��r.�G��e���sBBB!Y�4]��) G���g OҴʡi�͐�6QԼ�' �2wT�~��p嬙�z�q��ˆ8a�-��f^ˆҀ���L����E4�GX^�5�(�R�a���>���F�v"! �5�~>�]�,�~*2��n�M���>�i�A �B1U����<�R&��ϊz2�*FV�ѵ����Fm������Z5���~�r�T-�=� �1�7���pP��N �otg���dǟGo޶D�l�U����T��hp8��ε���n#ӊ�[y98��(�N!![p5 P�D! �� $8��r�#r�/;� �ȪD rTԨ�J��f�y��i.w�#�n ��k��V���#�b7]���|�^l61�w�ܼO�\�=�:`��s:=3��H��zJ3ʾJ*�Ղ�f����V�8�c0�pV[�u�!5��*ZRJFw�|�(�Ù���{���5$�8p �d$�A�J��rI���4��Gm������V�2����#2��Y N ��C��zy���+e-���q��H�]<�9�W{��%&��g��2���[���sq �U���f�Ӎ�<.���@�e=�$h�y��r��� ��vޢ���1���{.�%E�I�6�����L,��s���F�e`�Z�w5�� ��?� ���uzR��0U��?́o�i#���t��)�u[#�{M�9�q��劘�?�OdqOџv8���q>�}�c��Y�:E��U��tj/�i��#�7�yQl�����4��vUg�~;�h�� �@'�\�09�9���S�Z�Ӕ�K]��KE�8�l{�?V��ܪ��{ւ�ٱ�ԕ��zd�U�tD��~�*.j��[Du0=��w'�kR�q��z5 x: Dߘ���k��WYh�Y�OUg ���t�w*�>u��du�L'P�����O%���iuմ���=�JpvnZcm�^��OٱC%܌�`�����Ee�L�u���غ�^�owȭ�<2�����W���v�����[�KK_P*�_i�ͮ\A�Fl��h ŭ��K��r�E��;FB�qSUs�'�W�'v�ߴp?tës��`�bm;b��H�bN���q�A���u���ki�Ԕ4A�J���"Ƌ��36C[�sLM�k���⺖��/����z�(J+{���+�|��8Q��\����͎���g��ޫ#-s\�F@�d��CR��4;��Y,⍾[4m�1��m�>��4�9B�� .�%�WTm�w�����Z։n��+�vD! :�ZO��7����t�.�\����u0 x��K>Et61�g$�B�!@!@!T ���%�̭/ ��]Ȁy+)IF>�����Ů����;�+Y�p��xzqY�3��!r|�L����͛��O�ތ�G�{��snV/9���v{Cd˲�~JE�*T�Q����[�G���z?{� �T��pg�H�;��ϊzBHP�m�6��`�>�n>��V�G� qEh��S� ��h�rZ߭�ю+$g�� ����xU:3�4��M{�f���^'�ܰ�}�7�y$�u�V��R�s@z�Z05��4d�i�&�Эe-��6�5���]�v�a# %dU']\|��vv���~����TuN`u ��I�gn'������C\#�|j�>�t��"�3�� ��$��̈́��1��K�yƤ��;�'⦉�A ��4�B1*�J���ft{I}fɓ�� �n��n!>ۦ!���\�n�i��& �s���+>]%yŐ]�����G�8f(�m,v6�{s=� `�8:�`�G�;�à����6��`��?S(V�"6觼}��WW�lQ�p��J�l�ST]��0V��LX?��j�,��ԝc}��O�;C�)�v���,toe/�Ԩ�D��hhFí] K&��H륎l�b�+'�.��Hޛl�> j�c�woI�����`+�Jݶ�D���z'S�÷/�r�_�[A�i��7v��w/��@ ~��T�pɼ� ^�)�z34��$D ��R=�l�[�j�a��FGT&�ŧ6��V��H�S�ttY]%o�3��y O�Y�4ⴹ�����D��F���94�zx���]{ܾ+7��*;P�nX�E I7t�XW���4�KD��i���epS��B72U{)B3cZ`nc;����բ��F�<�72Bמ������\k��F��?��$-�F�� ��Z,�fHۯhsM*�4��FY��@цbP�\�ÎW:s@JE�.�������b��N�D�$d��w�]49oi��Z|Ŏu���+}�WC�6b| Ǵ�P[��ps��Q��`�����=�G6�c� �R]N&�&�Fƣ������u�� i�Yњ[�������n���eu� ~,�=�k�4d��Bז�������;���Q�˴Ѱ1����()�yT}4�5�pd&�i5��n�ZvN������eÔ�br�~^�6�����v�m���:���Q=�8���O���Pw8��汴gL,Ґ�(�]{K��<�G�����+,o��3^�暃]��j �E �i#;�Դ v�iz3ƃ� Ap&X.Iڤч~�vNBAMy�uf [��u@�v��3�5��$�V���5�����9��i?�72:ր7U����S~�"y$��Rv�C�+�5�NЋh������ �mt�+�4��*$Ұ!�1�����z��:*��3�l�sX�1���h�J�g��`{NTj#h#Q���yL�y�ڜ1,}d��h�qh�p�Eq��g,�f�����(���]'�E]�����S?y���O��G˽G� ��?�͓�$�Ew�4{���I�i=��o#�Ը�(��Ru��[�L�ܾ݉���e��������_�g��?�\oY������U�}'����A� ��������DU�e�����M�o��/.S��o�aVsd��H��a�2v8�����V琽셤� .q�"m/P�$����u/i���V�;��:���­�2��W��.�{uÖ����>���ô1���'2w�i L2 �W(�}d�9����� H�A�= �!�) �d�\D�������ԥ�f���j F�AA�p 䴖u�G��XHd����L����xb7�Ly5�X�����׳�G������a�����4���t9=KjIµ+���c�x7�Q���ߊ�!T*��� :ߣ��nb)�h+E�����̓�k�k��+MU�X� ���=�Л�Է&����ݽ����;��]��Xwj:���b��C�Z�i�>9��sRf��h����� ��y�NF��%Mn\���*TԵD*Tڥ@�SP��SR�Ir< ാ��=���|��$��\&����ʟ� ���].=�������ĴsX���U�6�����*�]q�T���s�]¾�%��> Ș������غ�C)[�x$���WL�(,P�6�m�� mķ�5��MJ`QU����3A��k�W�6 ��� �����p8��5�G��ߑ�8�8�㹠rZ�hm nM��\�/��R�D�45�Z(� 70�B��Ktu�/=uƨ�:n;�y[�)�4���Hʂ6�[yƙō?�4��P��;��Ini���l�CJ��_I��j�,m��A�)N ;o�?�o�+�ש���BQ]t�i�h�RQKu!��j.�HIu�D�W�'�EٴT�il�}YV�>�{[��������uV?Gض���.>�Ol�/�+�݌@�;� ��Kr#��yͮ N��R��b�4��f�+�N�������q���๮��'Z�hid/-m�/�����y+)���4��,�X��p0dC^��A��jk�h�|.��6݆�lu2?T��р�55�MJ�3lWL]U���C�g ��o �W���~���˯P�@H��H�۲�(rjD��OE��E�����˻L�9r��J�q�����hΝ?�b�)9�%2��׍k�(��p��D��l��8„�m 3�J�U��b���� 鵝��C+����p��;���Ŧ��L�J�6��VF���_�U�z���ϴ���I�U��"�������.�@f�I��f��8�R.��i��6�X�V���Ү�Yg�u&GK,.oU#X�H܉qp7{�h����@)�$����j���`�I��5�lQ����⊪�y f� �CҤJ��!%�\��o�:#�V�DkpVI=���h9�n�� ˾�gcm20�����u�p�kȯSj���姫�z�N �և�K�lg}�a�ⴴ��8_#�Ɨ8�h�y�EzGz�#d�Z]V{��o1�6�2;nG�4� ��[�Ⴐ����$�W1�� cƾEJ��'��S��[��Z�(i=��j�skq����1�mOF�,� �h�ܕ��0��1�P�v�a��6�N��ӆI���Ln�1�1���滑�x�l�x7�v���y���X���-�)���W�]�uN�P� � ��y�(U� a���m h&k�����(������gk� �1��M(]��7�v� �xi�K,a„,y"������j��<6V���Wm�' �c[]N ����@ܹ'U1���R��@�SR�T$�J�� &G�\5�}��� �Z�w�O�yfy��7�\O�\�n���=��(�.��v�OK��:�����2Q�q�� x�.ӦhC��=IU�ƙ��h��' �)��R��E�g��cuG!�i�}X� [K*����+�m+���F-=a�H難�����5� �p�U\���fd��#��Nh!fݪT׶�*" adL����edr8��߼�d��PKt�{\ ^�{.i��P��$l)�[�Ǎi�j�Y���8 5>��e�p'�D,8G����C������Ň�5ql���+u � ����Tv7�`;FK�� c��Tƫ�zQ�>�3�;���1�V��N>R�Ň�G'/�?�ƚZ�ˍI$�IQT�NB�2>m�6�o�K��rU�!��Ev�BiT�"�BH� � \ڧ!w2�VSKVt�D��k��p$�L��F�<QoG�� �����׍�9�Ts^���̞&L��Esx5��4�E�0�����VX�u~6�t<��sṷ~�t����O ������xR����Ů�\��Qk��� �'<��jpx���Go��R\�S.���Ë�ӯ#�: ���~�0'���t��ׁtsK��hd��4����=���^��{Z����i�EAS<|j㗔Q�E� �� b4���<��-KL�_��J6юÛoj�\�b�2m�9��Y��G�_������m�/�B����lo�H�aR93�o �=����Y#|�IBZ�h�c�5�a����sՈek���F �*N��$`sH ��2 �U7���?w+��:�!�t\�p�CP]x��c(�A)��Sj��qm> ���0:�c\�=��|����V��1�Q� ��j:�1 9c*�tx:�i�hAe p"��i��k�T�no�;�)Ri�w��WF�upJ��@�SR�pB@��6�j�R�Bˑ�W�WHv����o�v�8�uO��G`W3W.7����}:q�i=*�GĀ�,�7%(6��I�ݓ����xM�`8)����$��$�WfY,���64��4h�����^;(u$��^rf�ơ�3䎉�u�V_xg��9����N�р��ʐ59Q���4V[�4��M��X�L� 4纥5J� ����k�r4vdh����O*U�"�!����3C$�"��+G㌟6�G  �����Yt�Վ��2sN���ɉq�@#.�暁#?)��j5)[°�S1I��#��p�C�KKi#��'ǵ�^���/��LK[�7� �s�9�;ҭ�J���x�J)^�U�{'��EI����T4T�}�k�+ �~#��{j=�ﭑ��t�����\�A�/g�;���k��O��V��훧-Ή�k0|��� s����y.|G��W8���<έ�-��BKc�e�;��[_�+%g'���o��i�*V�@�#�TM��Ց�9��6��w ���ed��R l�N��M�)J������G�V�L�k?UQPK�#��(�/F᳓!d��dpȜ(���n��E���t� qX�"��Y#��t�}�`��v����FY�=҂ )`4|���]��xS. ȥr��ZFI�t�>�ƍMh��%{x0���͗� P�B�� � JS$U*B ���@!@!@!@QB!6��� ��-ςVM/F�µ��A�� �4�,�Yt�}k���X��6^�P�{��ӆV�&��u�F�v�Qmtg���g0��-.0�ݺ���jk��{�'j���H�W=�{��8ԯ.vd�$�Ҭkݺ%-ls�����|�Яn�A����dx9�g�x�Y��Ln$���)Z�sV4�cO�Y�F<~G��b��~�?� ���m%��w�џvH�)��bgH��,��f�%��B^�}��O�o�)��ү�����e�}۟Խ���.�c�$p������H�׆��u���5�x K#��.��P��i�vG0y4+��~�?�<1߳�O�~��-k�^�!|lq���q�HJZ�AT/S�Np�UgDXoG��E>;Q�y;_=�Xsy��C!��a�v�u��'9���k8v9�#��n���4 qћ���q x�nz��|���b�,�i�� ����x�we��R�EB!@$)Rn������z�x�F�-�pBF�8%E BD� �J��J��9%�<���.�Uͅ��Y)Y�$��j���b�7=�;qB���y�o �u�sV�^���qǷZF�t@�}nA�D�� ��!�k����6�C!Ƅސ���c��$/b� ֆ�ZA�P�t�yS��!e��!�!�!�!U )a�s($��7�sc�+�+��W�6y��Z�s]�k�k��P��Nٺ�[� ������zZ��X�PZ?) ��;u�\_K#w�~8�N�+A»n��lQ�]��$���]�IIC��#�kN ^�����C�<�i36���~ � ͺ?�Y�չ$o�� �Ů����^�����@ � �ZG�S�a��� m k�w �0�AA)�Ǔ,z�8�&�>��V0�Ƶw�ܵ����(7%U��-%��c�l�u�C{��&Yܻ^L�f���sZ֊�8�� 䬷[m���O�i�?x�\�L�g.{�+��1���\Ʀ�@ i�NB�s ��龝F�Yfi�� )���Cy\���\d��{��s�4��O*�N⤞�u�j.uMv⚄/���|ܮ�P�*���R � �!P$J���PMN@!*D��� �!%�D"��}��:�f�R��E�z�х�}RFS+�w1�� �x/7�O[v��^�������J�).���`����Hm�ROz'1���0�\���S٧��Q��g?W��ub{i��]ą��Ykhu�����c}���]|�*�'��ix�϶h|�*7�����!|��X�<2��H�g��k���=����8��4k1[v C/N���{Z p�ؘ�Mݧk�-��4������9B�v��y9r�^ɡt�v������4�� �V�^S�+��z�:��\�.�w�1�}X�ö���j�3ӿ��t��O!�_��C����&]����o��4 �����+���ľ�&Jw�X> �KO"��`��V �n=�a\{k?�UT�8%_F>aP�"�R ��@���P �P�B (Q�)�Oc��ÁBi ��� � � T!�R �F4�՟ q!����MN �w"|��Jr��j�7Wol�����C���R���1����[�x�B$?_����c�*n���i�W��������/(�ұ���ͻ#���q�H�� �L��V��u��/�^Ž8�Q���s�t���Zߎ�&�������y5ɖ�eA�f�7B� Y'xP�CBq`��C0ƻT�{��G�,�M� �B �#%�=�_Z��l��6<;�W�^$һߣM'G>�Nl~�x��T�5�z*AN ��Q�v~*D( d�ge���:³J��Pv&�\ ��j�F��4ێ��;A�9;楆F����ӟ-�{��-Mk@� ��*]�n��+ pp�MB�L��x�ɻ��Tdؾ���d���Fv�T��*;BBBD T!UҖ��3kG�L<胗^.q�r��^7��Wkh�3SX����U��v���7K�8��}h�̖��=K7G<�%���KJ������}^�T��/����d�c�f�*rBBBBB ��A�zF� �HBT �zi�ʗZ"���ƽkxH�v�? �C��%y�Mz1�8�aoٻ�h~ONƹ;$�^#�u�6!5��^���O�W1�.�]7F�`H��bw��\�GԮ�ݛ�p��]"�x{.�o�� �R5�S�i���څo��+��X;���Z2�M�*����FѬs^�l��9㓼�P����9���*E��cHQ�k�f�ٸs�Ժe���� ���\/N����>n?%��t���3��ަ-������´TV��1ߕ�� �=����؎ �(��} z|�T! �BD��E�4�d�\��T�R%Z@�!�* p�@�P� ���f��HF�/ԦM�&���! P"���T�A�У�g?����5^ �m� ��w#�����ndδ>9�m�����Ƹm����{z�o�;E�G��ݐ�g�>��`^Ch��^9�I�q>k��}%2��;Ee��q �i�� Y��8Uk� {g�=�2Q�pAM��Gխl|26X��y�8�TsUKT���z3�Yl��E�4�FV�]��A�~J�{��Od`9����}�q#kA����su��{.���Nװ�5��#"4\,Ӵ�qb9�=hZ� hv]�k�5���0�x�հ�+)2 R!C,�vNН��Ɂ��G��J�#� ���5�-f�=��{l�o`EA�*�2^��S�e� ��8!W6��4a��#��%Mn\���P�*)P�*D U��Ii`�I94�>M�Z�����6�k$y�KCԳ��5gl��dv�s$���W�~3�B?t���xooL�WC�z�tm���>�;G�i�z��}��M,�}�a���S��5�M q�:r�`!@!@!@!@!@!@!@��E�8q'!�=2��՝���Լ�=K���:�e�aX�A�489�c�j����^����EA0B��t}�I/�������a����<�r�9-6j�:��������+9�,"�� �������D������F{�=������t���P>�s=�?�Wn ����1�;T�Ŵ���j3�8|v��E����OS�Z�� �����-i�p��׆֓Q�Nn?/qǃ��껅���m� ��.�9�p �dAȮ?���B��0��ג=�L�6X�G.���Uev���$v����U/N]�:�T�uB�8_O��g�B�*D�6L�`��Dȃ.k?*�*D-!P� � D�F D�(���P��b�:��KI����#��+l��TB �B繬cK��5�hĹ�4s)��~��.jt��p �P�MGjPb��;ݹL���Α�&�|Խj���Y/:�/7�`] .��j+�y�^��"�[,���i�fY�s�ye��66��$V��;�W��蟭۠�f��d����R÷�;�X�.�:�����7���p�+�ccs�m ���(��fM�m���[,P0E ��|&)#!���� W"3"���aӯ��~� ����������hk�7�.f����*RK�����ߢ�IK~Z��]- G�TDӫi9�����o�Me�ء�9�Dz�$�8z��`@��k#�2� �^�C��Ѥ:�F�ܤ�� u�E��C������_m H� ��v?�m��W���.���8C��w�q澴��������$�T��Q��D�kFƁ�:E�g���u�GP�����;���yu�at.+�(�0s�y�?���{*G:��*k�E@�Ȃ����47N�J��UƐ�/�i#ۈ9�{��W��~.��Y�](׀施�[MU��Xu��7� B�T!"BD T!!!�Al�2F:7�9��X�qS��V� �m��$�2{.��89������,�������#d�#��]�����"tR �ÛN�4�!p�j7� l���G,&7bЇ��G G�'X�e��e���i9��x��#��D&�G`q�qR�|x+C��L��C�ѵ�7�#�1��:��F�fR�Ni��,�� TҔ��v)-�@�dto&�:��x���5�J�^^^?{�g.櫝R�M,���'b�r�c_?%�&��O]�H�D3R��5�����OBT����P�(�R �f�P�D*�,d�>7�NrUB�'jICِ��63����&��J�QD�J�E�e릊��t��xҍ���ܫU�I},�G >�����äu�Hb���#m���c7�$M &����Y;��دH�9饭���m��fN�/�5�`Z{ з���%�=� _[�u�{�{Ndv����kk�M6�p�'8H�ėd�%K��{F��>��9ͺ�lkh��n�N׹� ��.��h#G��� ��o��j�<ׇ &���0���R�3+�N���� ��4��kE�5~��:��5���A8�k!�c�c���i4�4T8ePuQ3E}� ~���GՏZ޺id��n!ΒS�2�٧|n��D�E#�}6^iY�O$���z�<�L��@VcQ�} t�i;`|U������H ���KC������Z��[\�7������^�����87ch��4��V��mC��y� ����81�������SPv?C�^8-��G Lmc 4k]V����` kj��cm|�2="���Z&��ZZ�� Mpk�ZV��Լ������7n ]�6���]���ˡԢ����.��M ���4{��V9��Z] d�ɥ#'�P Ay��ю�M�2e{#�ѭ܅M7*q���MN�v��I�HsIii����FE\q��諒*�-� f4� �5,�G�ZN׹� v��ql�#���G��=�|�t�q�U�$�¤�P��z7n�Ŗ)+RX���]� �5�;A�\ѕ��RBOݼ=����O����g�y�ˤ�f^�u8X-�fk�Zj�H�j��7��[uSr��]е��6,�M�ё�渐�iZjä�'d�\3�[�{��\���Б ��H���}㸡%�����i��R���U����P R!���?O�H u�[�Ok�C�=nŠ{O`�PO�+WN�YX�a�狍��5�+*|^����?Լ��n���I�v�vC�W�N�wh���u�6�^���H�� �`+UP������B?�+�n!"TFu�:;�*�ԴCxo,�q��&�4���ne>����L릏��#}���g�$�W�d����O�ZkC��;�г��;�dZ�aݶ�J`���=�c0���=��if����oٵ��Ӭs�. �sIk�X�=�0~#X:��q�yG�� Sh�[���u� -5i�GQ�E��вZE�Dq�ym��ਨߗ���+0��d����h:�|��F^�Qg�Ϡc\�a�^k�+�tz����f��U����q+ج�6F۱��h�Ɔ��'�Ayv�o���=��U�Y鹅��U�5��4{\ñ�->}�����##N��8x�sX�x�;��)�鯣�,��+g~�U�-9r!y�����~�>�h$e]��4^�9�qˎ�:l��Lb*�஻s�f,��ZL{Z�-�D%BH�R!*PN�j�)� �,X���D�.m,Œz�褕�[��:6WW$m�P�*U� �Ϊա�DJ,�J�!@�ZU�1VV�J� Hn��=Vq�KUa�*��U��aP�*���iCf��O�M��8��XK٘���S�=��lK��P ����,�ס"U�� �p�r#"3 #�J�>� $��,��ٚ�h!TB :����[���P���! 8"�!�M�T ��@�H�i;A��R���}��|�PaO)|�?Q����;#Оj�A2��kO�T�2�Cv o* �5����=��Axr��N3Qab�v��ඊ�N�����f��q��B��hWV��o��[p�B�U�`�F�YB��#��-4�p޳Ee٥c��ֶ�?j{QKќ����I�t��\e!�`����H�$��J��ؽ���q�.�|~_�˗�c�v�tf�k�b����iFKOgaܷ!���y�`��Nd� ���њe�Q��jy���������' ��|����Ci�T�)�"��PF�U�=��;�pۭ��u A�*2T!!!! �+I��v� �=D�`%$TBH� �񦲵t����K^�#�r;]�w��Y�lk&�Ĝ�㋜w�S�T>8�E�� ���FPIJ��M(�J�PR%B)r� p ��7�*D���;;8�_+}��?G�e�G��_�v(Ve~��}<���^�����`� �0�賭?Gv����s�m<׬ ��˔�f��^'i腽�ٞ�?�1�ɦ�*�a�<$�H��9��{�������T.��/�c�G�F4۫ܭ��K߳Ŏ���w�hV�����b�X�J�:5�ɟ,����$]�����߻|3x����y�+wG�p�%�V�����څ�r�~\�Q��%��չYѥ HH�*�1MS���Z�HJ��� P�6(�T))�@%H��!Q,L�h�q�P�U*˕U��<.��>#B�e ����:+�M���F��\��X� xK H¦SmK��֧,��[��,Rk�u��{.��5����@!@ �n?h�)Sm�x�(Zi�ܒ� VZB* Z��?/r?i���X0�"����t��y��F?N'��r\�.��c7UmN��a{ ���<�YF7 aZl'<�v�SO�w����ixރ^�v����޶}۽ҹ�Ci\J�^�:�h�g�5k,�>�X���/�ෂۅBBR�V���ɴV�� KLiN�]e#�@91�۷l�2�4�R�Ay�cuos�4.Y�|�"�\Mf����ku2��N<<�ޓ�?��H�ok#�&���@r ��(8���+N=ƴ4T묝�G%�ڨ}W���ݩ�NsH�Q5m��o|��ä́� ���ݑݚ�,V�L��5�9�c�����tn��\#2{�5�~T\98e�;z8��>�N��r�b� ��as#K6qB J������{��֣$#"�vYu^�YM��B�g��w��[�EB�@BHUEz�I��;@��H1�O�B���+Zi[C�?�w��`�B�{}���A�@7�P�@4���ɒ�r�d�D\Ƽ6[v�c�T V��s�*+te����Xk�r�f����������� hoXt��v{��{�q�Z|���)����-�y��� ����������鈕��)�� q:SQ$��5��8c�x���E�„l$� m/�J�"��Z�֙���1܆�oV�ު��N�J^+��z�:�����gY٭n�Vz���_�ӄ�+�����n��I,�[o����� Y��5��\m�b��1/cĮ��1� sh�I�Գ����.�Թw�n�K���Wڻ���XGS�:�\cv�-��%gYtV�&�v �rc��Gy[���U�5��.�4pc��M� �Fgvc h��G�FG�޹p۴u���۷kZ�V�������Q�u��S��ҧ�i����[��)~�ޏ_��Z�~>2��N���S?[O ��y�jk��8�lƮ|���#���T]lт'{�X��E�@{����c���dk:�M� ��|6Ԧb6QX��! �!*D��Ui�*�, R!eVXj�0�R�t�BsR�Q��FS��#=���}A]��Ϣٱ���w��%罽��QB� u��� -�x�(Zm}��ђ*��ڢ�9"Kȼ���q�q�-.<�W17q�����j�2V�������ǀ}��w�9��Nfh��ƃ̯?5�v�&ݭ����/�` g�<�Ȟ�qh�(�s��� �Q�M&~���q���.{ޱ;Gp�\J�N��z��G��}�:��Ē7���Ի+�i�(ro����6��(�RP`�4�����:�h�f� ��Z䫎� �-�g���8��~ �����q�ʮYLq�9,��Ӏ�FPǍݧ?2v-;4 ����$�gz��g m5�����V�c#Ŗ[�T�u=�YV�mq&�qZeb�08 w��RX�t�����mܝ�( iy��#0ѫ��֛M+��7X/�6��V�5�2�=�8�F Iߏ%cGC� ���м�������i�oX�M�aROy����vn.Y�����ol���f������ra��c�Ifsy����p���pW肼�e�w^�p��PT�N[�XY.���i��&�����8+V;[%e���� � Yi��vEH�é�� �S�0���+�Ll������i���M%�Xv:R+��^Y�@ޖ���!���Ni�/���4d��T$�@�M��ȣ�n�"��0斜������h�̔ޕ�i]u��%�7��� ����|�:���+xr���sϋ ���0�#�ˢ���@��,;�1�cZoґ���Z�WmV[�1�rD潍����o4���M֍�Ecv����_�q��g�(h��#� �X����A1a]s�3�U�,f�M�1��ch{��\��s�vF e��u���Q�7o�W.|򚩏���6� �ݩoi�P��p{Mx�,��@�flvGL�5βFe��ը5ִ����(��Ȭ�˖V���?�"�w�c��d��#�|�����GZ��9�vx��������/�X�+ a%��^>AX�[�ȥ�[�ȫy���x0�����D"7�q8��>��7��A sZ^{�n_-�ڇ�� �¸��'ZݾE'ZݾE\���j��a��= �kv�u���Wd� D�����$0ct1{�ɣd id���..�h$�p��YQ�<��hq���f�N�uQ\f�9]E���B\��<������ �V�e�ȠJݾEzdy�=7�n�"���|�!h�����ȣ�n�"�?Ih+5�Rx"�{�/��x�;L}��٤|S]Yb>=��W�u���Q}�|����n��΋�`�pVF�"��0�������+Mtf�k��]������Ϊ̇��$+�4�с�$��������y���HX�C����*�y�E�v+%H��R�$����Z�FBUWaP����~G���=�*�,BT�ZTX�෋5"�GjNs���R��A�'ih?����Ay��DB���X�ʏ?�!����Bm��Šz/�_ ���%���A�[��;����� N���