MINI Sh3ll

Path : /usr/src/linux-headers-5.15.0-138/arch/powerpc/include/asm/
File Upload :
Current File : //usr/src/linux-headers-5.15.0-138/arch/powerpc/include/asm/reg_booke.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Contains register definitions common to the Book E PowerPC
 * specification.  Notice that while the IBM-40x series of CPUs
 * are not true Book E PowerPCs, they borrowed a number of features
 * before Book E was finalized, and are included here as well.  Unfortunately,
 * they sometimes used different locations than true Book E CPUs did.
 *
 * Copyright 2009-2010 Freescale Semiconductor, Inc.
 */
#ifdef __KERNEL__
#ifndef __ASM_POWERPC_REG_BOOKE_H__
#define __ASM_POWERPC_REG_BOOKE_H__

#include <asm/ppc-opcode.h>

/* Machine State Register (MSR) Fields */
#define MSR_GS_LG	28	/* Guest state */
#define MSR_UCLE_LG	26	/* User-mode cache lock enable */
#define MSR_SPE_LG	25	/* Enable SPE */
#define MSR_DWE_LG	10	/* Debug Wait Enable */
#define MSR_UBLE_LG	10	/* BTB lock enable (e500) */
#define MSR_IS_LG	MSR_IR_LG /* Instruction Space */
#define MSR_DS_LG	MSR_DR_LG /* Data Space */
#define MSR_PMM_LG	2	/* Performance monitor mark bit */
#define MSR_CM_LG	31	/* Computation Mode (0=32-bit, 1=64-bit) */

#define MSR_GS		__MASK(MSR_GS_LG)
#define MSR_UCLE	__MASK(MSR_UCLE_LG)
#define MSR_SPE		__MASK(MSR_SPE_LG)
#define MSR_DWE		__MASK(MSR_DWE_LG)
#define MSR_UBLE	__MASK(MSR_UBLE_LG)
#define MSR_IS		__MASK(MSR_IS_LG)
#define MSR_DS		__MASK(MSR_DS_LG)
#define MSR_PMM		__MASK(MSR_PMM_LG)
#define MSR_CM		__MASK(MSR_CM_LG)

#if defined(CONFIG_PPC_BOOK3E_64)
#define MSR_64BIT	MSR_CM

#define MSR_		(MSR_ME | MSR_RI | MSR_CE)
#define MSR_KERNEL	(MSR_ | MSR_64BIT)
#define MSR_USER32	(MSR_ | MSR_PR | MSR_EE)
#define MSR_USER64	(MSR_USER32 | MSR_64BIT)
#elif defined (CONFIG_40x)
#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
#else
#define MSR_KERNEL	(MSR_ME|MSR_RI|MSR_CE)
#define MSR_USER	(MSR_KERNEL|MSR_PR|MSR_EE)
#endif

/* Special Purpose Registers (SPRNs)*/
#define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
#define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
#define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
#define SPRN_SPRG3R	0x103	/* Special Purpose Register General 3 Read */
#define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
#define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
#define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
#define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
#define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
#define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
#define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
#define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
#define SPRN_EPCR	0x133	/* Embedded Processor Control Register */
#define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
#define SPRN_DBCR4	0x233	/* Debug Control Register 4 */
#define SPRN_MSRP	0x137	/* MSR Protect Register */
#define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
#define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
#define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
#define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
#define SPRN_LPID	0x152	/* Logical Partition ID */
#define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
#define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
#define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
#define SPRN_MAS5_MAS6	0x15c	/* MMU Assist Register 5 || 6 */
#define SPRN_MAS8_MAS1	0x15d	/* MMU Assist Register 8 || 1 */
#define SPRN_EPTCFG	0x15e	/* Embedded Page Table Config */
#define SPRN_GSPRG0	0x170	/* Guest SPRG0 */
#define SPRN_GSPRG1	0x171	/* Guest SPRG1 */
#define SPRN_GSPRG2	0x172	/* Guest SPRG2 */
#define SPRN_GSPRG3	0x173	/* Guest SPRG3 */
#define SPRN_MAS7_MAS3	0x174	/* MMU Assist Register 7 || 3 */
#define SPRN_MAS0_MAS1	0x175	/* MMU Assist Register 0 || 1 */
#define SPRN_GSRR0	0x17A	/* Guest SRR0 */
#define SPRN_GSRR1	0x17B	/* Guest SRR1 */
#define SPRN_GEPR	0x17C	/* Guest EPR */
#define SPRN_GDEAR	0x17D	/* Guest DEAR */
#define SPRN_GPIR	0x17E	/* Guest PIR */
#define SPRN_GESR	0x17F	/* Guest Exception Syndrome Register */
#define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
#define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
#define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
#define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
#define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
#define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
#define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
#define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
#define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
#define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
#define SPRN_IVOR10	0x19A	/* Interrupt Vector Offset Register 10 */
#define SPRN_IVOR11	0x19B	/* Interrupt Vector Offset Register 11 */
#define SPRN_IVOR12	0x19C	/* Interrupt Vector Offset Register 12 */
#define SPRN_IVOR13	0x19D	/* Interrupt Vector Offset Register 13 */
#define SPRN_IVOR14	0x19E	/* Interrupt Vector Offset Register 14 */
#define SPRN_IVOR15	0x19F	/* Interrupt Vector Offset Register 15 */
#define SPRN_IVOR38	0x1B0	/* Interrupt Vector Offset Register 38 */
#define SPRN_IVOR39	0x1B1	/* Interrupt Vector Offset Register 39 */
#define SPRN_IVOR40	0x1B2	/* Interrupt Vector Offset Register 40 */
#define SPRN_IVOR41	0x1B3	/* Interrupt Vector Offset Register 41 */
#define SPRN_IVOR42	0x1B4	/* Interrupt Vector Offset Register 42 */
#define SPRN_GIVOR2	0x1B8	/* Guest IVOR2 */
#define SPRN_GIVOR3	0x1B9	/* Guest IVOR3 */
#define SPRN_GIVOR4	0x1BA	/* Guest IVOR4 */
#define SPRN_GIVOR8	0x1BB	/* Guest IVOR8 */
#define SPRN_GIVOR13	0x1BC	/* Guest IVOR13 */
#define SPRN_GIVOR14	0x1BD	/* Guest IVOR14 */
#define SPRN_GIVPR	0x1BF	/* Guest IVPR */
#define SPRN_SPEFSCR	0x200	/* SPE & Embedded FP Status & Control */
#define SPRN_BBEAR	0x201	/* Branch Buffer Entry Address Register */
#define SPRN_BBTAR	0x202	/* Branch Buffer Target Address Register */
#define SPRN_L1CFG0	0x203	/* L1 Cache Configure Register 0 */
#define SPRN_L1CFG1	0x204	/* L1 Cache Configure Register 1 */
#define SPRN_ATB	0x20E	/* Alternate Time Base */
#define SPRN_ATBL	0x20E	/* Alternate Time Base Lower */
#define SPRN_ATBU	0x20F	/* Alternate Time Base Upper */
#define SPRN_IVOR32	0x210	/* Interrupt Vector Offset Register 32 */
#define SPRN_IVOR33	0x211	/* Interrupt Vector Offset Register 33 */
#define SPRN_IVOR34	0x212	/* Interrupt Vector Offset Register 34 */
#define SPRN_IVOR35	0x213	/* Interrupt Vector Offset Register 35 */
#define SPRN_IVOR36	0x214	/* Interrupt Vector Offset Register 36 */
#define SPRN_IVOR37	0x215	/* Interrupt Vector Offset Register 37 */
#define SPRN_MCARU	0x239	/* Machine Check Address Register Upper */
#define SPRN_MCSRR0	0x23A	/* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1	0x23B	/* Machine Check Save and Restore Register 1 */
#define SPRN_MCSR	0x23C	/* Machine Check Status Register */
#define SPRN_MCAR	0x23D	/* Machine Check Address Register */
#define SPRN_DSRR0	0x23E	/* Debug Save and Restore Register 0 */
#define SPRN_DSRR1	0x23F	/* Debug Save and Restore Register 1 */
#define SPRN_SPRG8	0x25C	/* Special Purpose Register General 8 */
#define SPRN_SPRG9	0x25D	/* Special Purpose Register General 9 */
#define SPRN_L1CSR2	0x25E	/* L1 Cache Control and Status Register 2 */
#define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
#define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
#define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
#define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
#define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
#define SPRN_MAS5	0x153	/* MMU Assist Register 5 */
#define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
#define SPRN_PID1	0x279	/* Process ID Register 1 */
#define SPRN_PID2	0x27A	/* Process ID Register 2 */
#define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
#define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
#define SPRN_TLB2CFG	0x2B2	/* TLB 2 Config Register */
#define SPRN_TLB3CFG	0x2B3	/* TLB 3 Config Register */
#define SPRN_EPR	0x2BE	/* External Proxy Register */
#define SPRN_CCR1	0x378	/* Core Configuration Register 1 */
#define SPRN_ZPR	0x3B0	/* Zone Protection Register (40x) */
#define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
#define SPRN_MMUCR	0x3B2	/* MMU Control Register */
#define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
#define SPRN_EPLC	0x3B3	/* External Process ID Load Context */
#define SPRN_EPSC	0x3B4	/* External Process ID Store Context */
#define SPRN_SGR	0x3B9	/* Storage Guarded Register */
#define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
#define SPRN_SLER	0x3BB	/* Little-endian real mode */
#define SPRN_SU0R	0x3BC	/* "User 0" real mode (40x) */
#define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
#define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
#define SPRN_L1CSR0	0x3F2	/* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR1	0x3F3	/* L1 Cache Control and Status Register 1 */
#define SPRN_MMUCSR0	0x3F4	/* MMU Control and Status Register 0 */
#define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
#define SPRN_BUCSR	0x3F5	/* Branch Unit Control and Status */
#define SPRN_L2CSR0	0x3F9	/* L2 Data Cache Control and Status Register 0 */
#define SPRN_L2CSR1	0x3FA	/* L2 Data Cache Control and Status Register 1 */
#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
#define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
#define SPRN_PWRMGTCR0	0x3FB	/* Power management control register 0 */
#define SPRN_SVR	0x3FF	/* System Version Register */

/*
 * SPRs which have conflicting definitions on true Book E versus classic,
 * or IBM 40x.
 */
#ifdef CONFIG_BOOKE
#define SPRN_CSRR0	0x03A	/* Critical Save and Restore Register 0 */
#define SPRN_CSRR1	0x03B	/* Critical Save and Restore Register 1 */
#define SPRN_DEAR	0x03D	/* Data Error Address Register */
#define SPRN_ESR	0x03E	/* Exception Syndrome Register */
#define SPRN_PIR	0x11E	/* Processor Identification Register */
#define SPRN_DBSR	0x130	/* Debug Status Register */
#define SPRN_DBCR0	0x134	/* Debug Control Register 0 */
#define SPRN_DBCR1	0x135	/* Debug Control Register 1 */
#define SPRN_IAC1	0x138	/* Instruction Address Compare 1 */
#define SPRN_IAC2	0x139	/* Instruction Address Compare 2 */
#define SPRN_DAC1	0x13C	/* Data Address Compare 1 */
#define SPRN_DAC2	0x13D	/* Data Address Compare 2 */
#define SPRN_TSR	0x150	/* Timer Status Register */
#define SPRN_TCR	0x154	/* Timer Control Register */
#endif /* Book E */
#ifdef CONFIG_40x
#define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */		
#define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
#define SPRN_DEAR	0x3D5	/* Data Error Address Register */
#define SPRN_TSR	0x3D8	/* Timer Status Register */
#define SPRN_TCR	0x3DA	/* Timer Control Register */
#define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
#define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
#define SPRN_DBSR	0x3F0	/* Debug Status Register */		
#define SPRN_DBCR0	0x3F2	/* Debug Control Register 0 */
#define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
#define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
#define SPRN_CSRR0	SPRN_SRR2 /* Critical Save and Restore Register 0 */
#define SPRN_CSRR1	SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif
#define SPRN_HACOP	0x15F	/* Hypervisor Available Coprocessor Register */

/* Bit definitions for CCR1. */
#define	CCR1_DPC	0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
#define	CCR1_TCS	0x00000080 /* Timer Clock Select */

/* Bit definitions for PWRMGTCR0. */
#define PWRMGTCR0_PW20_WAIT		(1 << 14) /* PW20 state enable bit */
#define PWRMGTCR0_PW20_ENT_SHIFT	8
#define PWRMGTCR0_PW20_ENT		0x3F00
#define PWRMGTCR0_AV_IDLE_PD_EN		(1 << 22) /* Altivec idle enable */
#define PWRMGTCR0_AV_IDLE_CNT_SHIFT	16
#define PWRMGTCR0_AV_IDLE_CNT		0x3F0000

/* Bit definitions for the MCSR. */
#define MCSR_MCS	0x80000000 /* Machine Check Summary */
#define MCSR_IB		0x40000000 /* Instruction PLB Error */
#define MCSR_DRB	0x20000000 /* Data Read PLB Error */
#define MCSR_DWB	0x10000000 /* Data Write PLB Error */
#define MCSR_TLBP	0x08000000 /* TLB Parity Error */
#define MCSR_ICP	0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP	0x02000000 /* D-Cache Search Parity Error */
#define MCSR_DCFP	0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE	0x00800000 /* Imprecise Machine Check Exception */

#define PPC47x_MCSR_GPR	0x01000000 /* GPR parity error */
#define PPC47x_MCSR_FPR	0x00800000 /* FPR parity error */
#define PPC47x_MCSR_IPR	0x00400000 /* Imprecise Machine Check Exception */

#ifdef CONFIG_E500
/* All e500 */
#define MCSR_MCP 	0x80000000UL /* Machine Check Input Pin */
#define MCSR_ICPERR 	0x40000000UL /* I-Cache Parity Error */

/* e500v1/v2 */
#define MCSR_DCP_PERR 	0x20000000UL /* D-Cache Push Parity Error */
#define MCSR_DCPERR 	0x10000000UL /* D-Cache Parity Error */
#define MCSR_BUS_IAERR 	0x00000080UL /* Instruction Address Error */
#define MCSR_BUS_RAERR 	0x00000040UL /* Read Address Error */
#define MCSR_BUS_WAERR 	0x00000020UL /* Write Address Error */
#define MCSR_BUS_IBERR 	0x00000010UL /* Instruction Data Error */
#define MCSR_BUS_RBERR 	0x00000008UL /* Read Data Bus Error */
#define MCSR_BUS_WBERR 	0x00000004UL /* Write Data Bus Error */
#define MCSR_BUS_IPERR 	0x00000002UL /* Instruction parity Error */
#define MCSR_BUS_RPERR 	0x00000001UL /* Read parity Error */

/* e500mc */
#define MCSR_DCPERR_MC	0x20000000UL /* D-Cache Parity Error */
#define MCSR_L2MMU_MHIT	0x08000000UL /* Hit on multiple TLB entries */
#define MCSR_NMI	0x00100000UL /* Non-Maskable Interrupt */
#define MCSR_MAV	0x00080000UL /* MCAR address valid */
#define MCSR_MEA	0x00040000UL /* MCAR is effective address */
#define MCSR_IF		0x00010000UL /* Instruction Fetch */
#define MCSR_LD		0x00008000UL /* Load */
#define MCSR_ST		0x00004000UL /* Store */
#define MCSR_LDG	0x00002000UL /* Guarded Load */
#define MCSR_TLBSYNC	0x00000002UL /* Multiple tlbsyncs detected */
#define MCSR_BSL2_ERR	0x00000001UL /* Backside L2 cache error */

#define MSRP_UCLEP	0x04000000 /* Protect MSR[UCLE] */
#define MSRP_DEP	0x00000200 /* Protect MSR[DE] */
#define MSRP_PMMP	0x00000004 /* Protect MSR[PMM] */
#endif

/* Bit definitions for the HID1 */
#ifdef CONFIG_E500
/* e500v1/v2 */
#define HID1_PLL_CFG_MASK 0xfc000000	/* PLL_CFG input pins */
#define HID1_RFXE	0x00020000	/* Read fault exception enable */
#define HID1_R1DPE	0x00008000	/* R1 data bus parity enable */
#define HID1_R2DPE	0x00004000	/* R2 data bus parity enable */
#define HID1_ASTME	0x00002000	/* Address bus streaming mode enable */
#define HID1_ABE	0x00001000	/* Address broadcast enable */
#define HID1_MPXTT	0x00000400	/* MPX re-map transfer type */
#define HID1_ATS	0x00000080	/* Atomic status */
#define HID1_MID_MASK	0x0000000f	/* MID input pins */
#endif

/* Bit definitions for the DBSR. */
/*
 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
 */
#ifdef CONFIG_BOOKE
#define DBSR_IDE	0x80000000	/* Imprecise Debug Event */
#define DBSR_MRR	0x30000000	/* Most Recent Reset */
#define DBSR_IC		0x08000000	/* Instruction Completion */
#define DBSR_BT		0x04000000	/* Branch Taken */
#define DBSR_IRPT	0x02000000	/* Exception Debug Event */
#define DBSR_TIE	0x01000000	/* Trap Instruction Event */
#define DBSR_IAC1	0x00800000	/* Instr Address Compare 1 Event */
#define DBSR_IAC2	0x00400000	/* Instr Address Compare 2 Event */
#define DBSR_IAC3	0x00200000	/* Instr Address Compare 3 Event */
#define DBSR_IAC4	0x00100000	/* Instr Address Compare 4 Event */
#define DBSR_DAC1R	0x00080000	/* Data Addr Compare 1 Read Event */
#define DBSR_DAC1W	0x00040000	/* Data Addr Compare 1 Write Event */
#define DBSR_DAC2R	0x00020000	/* Data Addr Compare 2 Read Event */
#define DBSR_DAC2W	0x00010000	/* Data Addr Compare 2 Write Event */
#define DBSR_RET	0x00008000	/* Return Debug Event */
#define DBSR_CIRPT	0x00000040	/* Critical Interrupt Taken Event */
#define DBSR_CRET	0x00000020	/* Critical Return Debug Event */
#define DBSR_IAC12ATS	0x00000002	/* Instr Address Compare 1/2 Toggle */
#define DBSR_IAC34ATS	0x00000001	/* Instr Address Compare 3/4 Toggle */
#endif
#ifdef CONFIG_40x
#define DBSR_IC		0x80000000	/* Instruction Completion */
#define DBSR_BT		0x40000000	/* Branch taken */
#define DBSR_IRPT	0x20000000	/* Exception Debug Event */
#define DBSR_TIE	0x10000000	/* Trap Instruction debug Event */
#define DBSR_IAC1	0x04000000	/* Instruction Address Compare 1 Event */
#define DBSR_IAC2	0x02000000	/* Instruction Address Compare 2 Event */
#define DBSR_IAC3	0x00080000	/* Instruction Address Compare 3 Event */
#define DBSR_IAC4	0x00040000	/* Instruction Address Compare 4 Event */
#define DBSR_DAC1R	0x01000000	/* Data Address Compare 1 Read Event */
#define DBSR_DAC1W	0x00800000	/* Data Address Compare 1 Write Event */
#define DBSR_DAC2R	0x00400000	/* Data Address Compare 2 Read Event */
#define DBSR_DAC2W	0x00200000	/* Data Address Compare 2 Write Event */
#endif

/* Bit definitions related to the ESR. */
#define ESR_MCI		0x80000000	/* Machine Check - Instruction */
#define ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
#define ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
#define ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
#define ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
#define ESR_PIL		0x08000000	/* Program Exception - Illegal */
#define ESR_PPR		0x04000000	/* Program Exception - Privileged */
#define ESR_PTR		0x02000000	/* Program Exception - Trap */
#define ESR_FP		0x01000000	/* Floating Point Operation */
#define ESR_DST		0x00800000	/* Storage Exception - Data miss */
#define ESR_DIZ		0x00400000	/* Storage Exception - Zone fault */
#define ESR_ST		0x00800000	/* Store Operation */
#define ESR_DLK		0x00200000	/* Data Cache Locking */
#define ESR_ILK		0x00100000	/* Instr. Cache Locking */
#define ESR_PUO		0x00040000	/* Unimplemented Operation exception */
#define ESR_BO		0x00020000	/* Byte Ordering */
#define ESR_SPV		0x00000080	/* Signal Processing operation */

/* Bit definitions related to the DBCR0. */
#if defined(CONFIG_40x)
#define DBCR0_EDM	0x80000000	/* External Debug Mode */
#define DBCR0_IDM	0x40000000	/* Internal Debug Mode */
#define DBCR0_RST	0x30000000	/* all the bits in the RST field */
#define DBCR0_RST_SYSTEM 0x30000000	/* System Reset */
#define DBCR0_RST_CHIP	0x20000000	/* Chip Reset */
#define DBCR0_RST_CORE	0x10000000	/* Core Reset */
#define DBCR0_RST_NONE	0x00000000	/* No Reset */
#define DBCR0_IC	0x08000000	/* Instruction Completion */
#define DBCR0_ICMP	DBCR0_IC
#define DBCR0_BT	0x04000000	/* Branch Taken */
#define DBCR0_BRT	DBCR0_BT
#define DBCR0_EDE	0x02000000	/* Exception Debug Event */
#define DBCR0_IRPT	DBCR0_EDE
#define DBCR0_TDE	0x01000000	/* TRAP Debug Event */
#define DBCR0_IA1	0x00800000	/* Instr Addr compare 1 enable */
#define DBCR0_IAC1	DBCR0_IA1
#define DBCR0_IA2	0x00400000	/* Instr Addr compare 2 enable */
#define DBCR0_IAC2	DBCR0_IA2
#define DBCR0_IA12	0x00200000	/* Instr Addr 1-2 range enable */
#define DBCR0_IA12X	0x00100000	/* Instr Addr 1-2 range eXclusive */
#define DBCR0_IA3	0x00080000	/* Instr Addr compare 3 enable */
#define DBCR0_IAC3	DBCR0_IA3
#define DBCR0_IA4	0x00040000	/* Instr Addr compare 4 enable */
#define DBCR0_IAC4	DBCR0_IA4
#define DBCR0_IA34	0x00020000	/* Instr Addr 3-4 range Enable */
#define DBCR0_IA34X	0x00010000	/* Instr Addr 3-4 range eXclusive */
#define DBCR0_IA12T	0x00008000	/* Instr Addr 1-2 range Toggle */
#define DBCR0_IA34T	0x00004000	/* Instr Addr 3-4 range Toggle */
#define DBCR0_FT	0x00000001	/* Freeze Timers on debug event */

#define dbcr_iac_range(task)	((task)->thread.debug.dbcr0)
#define DBCR_IAC12I	DBCR0_IA12			/* Range Inclusive */
#define DBCR_IAC12X	(DBCR0_IA12 | DBCR0_IA12X)	/* Range Exclusive */
#define DBCR_IAC12MODE	(DBCR0_IA12 | DBCR0_IA12X)	/* IAC 1-2 Mode Bits */
#define DBCR_IAC34I	DBCR0_IA34			/* Range Inclusive */
#define DBCR_IAC34X	(DBCR0_IA34 | DBCR0_IA34X)	/* Range Exclusive */
#define DBCR_IAC34MODE	(DBCR0_IA34 | DBCR0_IA34X)	/* IAC 3-4 Mode Bits */

/* Bit definitions related to the DBCR1. */
#define DBCR1_DAC1R	0x80000000	/* DAC1 Read Debug Event */
#define DBCR1_DAC2R	0x40000000	/* DAC2 Read Debug Event */
#define DBCR1_DAC1W	0x20000000	/* DAC1 Write Debug Event */
#define DBCR1_DAC2W	0x10000000	/* DAC2 Write Debug Event */

#define dbcr_dac(task)	((task)->thread.debug.dbcr1)
#define DBCR_DAC1R	DBCR1_DAC1R
#define DBCR_DAC1W	DBCR1_DAC1W
#define DBCR_DAC2R	DBCR1_DAC2R
#define DBCR_DAC2W	DBCR1_DAC2W

/*
 * Are there any active Debug Events represented in the
 * Debug Control Registers?
 */
#define DBCR0_ACTIVE_EVENTS	(DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
				 DBCR0_IAC3 | DBCR0_IAC4)
#define DBCR1_ACTIVE_EVENTS	(DBCR1_DAC1R | DBCR1_DAC2R | \
				 DBCR1_DAC1W | DBCR1_DAC2W)
#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
					   ((dbcr1) & DBCR1_ACTIVE_EVENTS))

#elif defined(CONFIG_BOOKE)
#define DBCR0_EDM	0x80000000	/* External Debug Mode */
#define DBCR0_IDM	0x40000000	/* Internal Debug Mode */
#define DBCR0_RST	0x30000000	/* all the bits in the RST field */
/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
#define DBCR0_RST_SYSTEM 0x30000000	/* System Reset */
#define DBCR0_RST_CHIP	0x20000000	/* Chip Reset */
#define DBCR0_RST_CORE	0x10000000	/* Core Reset */
#define DBCR0_RST_NONE	0x00000000	/* No Reset */
#define DBCR0_ICMP	0x08000000	/* Instruction Completion */
#define DBCR0_IC	DBCR0_ICMP
#define DBCR0_BRT	0x04000000	/* Branch Taken */
#define DBCR0_BT	DBCR0_BRT
#define DBCR0_IRPT	0x02000000	/* Exception Debug Event */
#define DBCR0_TDE	0x01000000	/* TRAP Debug Event */
#define DBCR0_TIE	DBCR0_TDE
#define DBCR0_IAC1	0x00800000	/* Instr Addr compare 1 enable */
#define DBCR0_IAC2	0x00400000	/* Instr Addr compare 2 enable */
#define DBCR0_IAC3	0x00200000	/* Instr Addr compare 3 enable */
#define DBCR0_IAC4	0x00100000	/* Instr Addr compare 4 enable */
#define DBCR0_DAC1R	0x00080000	/* DAC 1 Read enable */
#define DBCR0_DAC1W	0x00040000	/* DAC 1 Write enable */
#define DBCR0_DAC2R	0x00020000	/* DAC 2 Read enable */
#define DBCR0_DAC2W	0x00010000	/* DAC 2 Write enable */
#define DBCR0_RET	0x00008000	/* Return Debug Event */
#define DBCR0_CIRPT	0x00000040	/* Critical Interrupt Taken Event */
#define DBCR0_CRET	0x00000020	/* Critical Return Debug Event */
#define DBCR0_FT	0x00000001	/* Freeze Timers on debug event */

#define dbcr_dac(task)	((task)->thread.debug.dbcr0)
#define DBCR_DAC1R	DBCR0_DAC1R
#define DBCR_DAC1W	DBCR0_DAC1W
#define DBCR_DAC2R	DBCR0_DAC2R
#define DBCR_DAC2W	DBCR0_DAC2W

/* Bit definitions related to the DBCR1. */
#define DBCR1_IAC1US	0xC0000000	/* Instr Addr Cmp 1 Sup/User   */
#define DBCR1_IAC1ER	0x30000000	/* Instr Addr Cmp 1 Eff/Real */
#define DBCR1_IAC1ER_01	0x10000000	/* reserved */
#define DBCR1_IAC1ER_10	0x20000000	/* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
#define DBCR1_IAC1ER_11	0x30000000	/* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
#define DBCR1_IAC2US	0x0C000000	/* Instr Addr Cmp 2 Sup/User   */
#define DBCR1_IAC2ER	0x03000000	/* Instr Addr Cmp 2 Eff/Real */
#define DBCR1_IAC2ER_01	0x01000000	/* reserved */
#define DBCR1_IAC2ER_10	0x02000000	/* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
#define DBCR1_IAC2ER_11	0x03000000	/* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
#define DBCR1_IAC12M	0x00800000	/* Instr Addr 1-2 range enable */
#define DBCR1_IAC12MX	0x00C00000	/* Instr Addr 1-2 range eXclusive */
#define DBCR1_IAC12AT	0x00010000	/* Instr Addr 1-2 range Toggle */
#define DBCR1_IAC3US	0x0000C000	/* Instr Addr Cmp 3 Sup/User   */
#define DBCR1_IAC3ER	0x00003000	/* Instr Addr Cmp 3 Eff/Real */
#define DBCR1_IAC3ER_01	0x00001000	/* reserved */
#define DBCR1_IAC3ER_10	0x00002000	/* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
#define DBCR1_IAC3ER_11	0x00003000	/* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
#define DBCR1_IAC4US	0x00000C00	/* Instr Addr Cmp 4 Sup/User   */
#define DBCR1_IAC4ER	0x00000300	/* Instr Addr Cmp 4 Eff/Real */
#define DBCR1_IAC4ER_01	0x00000100	/* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
#define DBCR1_IAC4ER_10	0x00000200	/* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
#define DBCR1_IAC4ER_11	0x00000300	/* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
#define DBCR1_IAC34M	0x00000080	/* Instr Addr 3-4 range enable */
#define DBCR1_IAC34MX	0x000000C0	/* Instr Addr 3-4 range eXclusive */
#define DBCR1_IAC34AT	0x00000001	/* Instr Addr 3-4 range Toggle */

#define dbcr_iac_range(task)	((task)->thread.debug.dbcr1)
#define DBCR_IAC12I	DBCR1_IAC12M	/* Range Inclusive */
#define DBCR_IAC12X	DBCR1_IAC12MX	/* Range Exclusive */
#define DBCR_IAC12MODE	DBCR1_IAC12MX	/* IAC 1-2 Mode Bits */
#define DBCR_IAC34I	DBCR1_IAC34M	/* Range Inclusive */
#define DBCR_IAC34X	DBCR1_IAC34MX	/* Range Exclusive */
#define DBCR_IAC34MODE	DBCR1_IAC34MX	/* IAC 3-4 Mode Bits */

/* Bit definitions related to the DBCR2. */
#define DBCR2_DAC1US	0xC0000000	/* Data Addr Cmp 1 Sup/User   */
#define DBCR2_DAC1ER	0x30000000	/* Data Addr Cmp 1 Eff/Real */
#define DBCR2_DAC2US	0x0C000000	/* Data Addr Cmp 2 Sup/User   */
#define DBCR2_DAC2ER	0x03000000	/* Data Addr Cmp 2 Eff/Real */
#define DBCR2_DAC12M	0x00800000	/* DAC 1-2 range enable */
#define DBCR2_DAC12MM	0x00400000	/* DAC 1-2 Mask mode*/
#define DBCR2_DAC12MX	0x00C00000	/* DAC 1-2 range eXclusive */
#define DBCR2_DAC12MODE	0x00C00000	/* DAC 1-2 Mode Bits */
#define DBCR2_DAC12A	0x00200000	/* DAC 1-2 Asynchronous */
#define DBCR2_DVC1M	0x000C0000	/* Data Value Comp 1 Mode */
#define DBCR2_DVC1M_SHIFT	18	/* # of bits to shift DBCR2_DVC1M */
#define DBCR2_DVC2M	0x00030000	/* Data Value Comp 2 Mode */
#define DBCR2_DVC2M_SHIFT	16	/* # of bits to shift DBCR2_DVC2M */
#define DBCR2_DVC1BE	0x00000F00	/* Data Value Comp 1 Byte */
#define DBCR2_DVC1BE_SHIFT	8	/* # of bits to shift DBCR2_DVC1BE */
#define DBCR2_DVC2BE	0x0000000F	/* Data Value Comp 2 Byte */
#define DBCR2_DVC2BE_SHIFT	0	/* # of bits to shift DBCR2_DVC2BE */

/*
 * Are there any active Debug Events represented in the
 * Debug Control Registers?
 */
#define DBCR0_ACTIVE_EVENTS  (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
			      DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
			      DBCR0_DAC1W  | DBCR0_DAC2R | DBCR0_DAC2W)
#define DBCR1_ACTIVE_EVENTS	0

#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
					   ((dbcr1) & DBCR1_ACTIVE_EVENTS))
#endif /* #elif defined(CONFIG_BOOKE) */

/* Bit definitions related to the TCR. */
#define TCR_WP(x)	(((x)&0x3)<<30)	/* WDT Period */
#define TCR_WP_MASK	TCR_WP(3)
#define WP_2_17		0		/* 2^17 clocks */
#define WP_2_21		1		/* 2^21 clocks */
#define WP_2_25		2		/* 2^25 clocks */
#define WP_2_29		3		/* 2^29 clocks */
#define TCR_WRC(x)	(((x)&0x3)<<28)	/* WDT Reset Control */
#define TCR_WRC_MASK	TCR_WRC(3)
#define WRC_NONE	0		/* No reset will occur */
#define WRC_CORE	1		/* Core reset will occur */
#define WRC_CHIP	2		/* Chip reset will occur */
#define WRC_SYSTEM	3		/* System reset will occur */
#define TCR_WIE		0x08000000	/* WDT Interrupt Enable */
#define TCR_PIE		0x04000000	/* PIT Interrupt Enable */
#define TCR_DIE		TCR_PIE		/* DEC Interrupt Enable */
#define TCR_FP(x)	(((x)&0x3)<<24)	/* FIT Period */
#define TCR_FP_MASK	TCR_FP(3)
#define FP_2_9		0		/* 2^9 clocks */
#define FP_2_13		1		/* 2^13 clocks */
#define FP_2_17		2		/* 2^17 clocks */
#define FP_2_21		3		/* 2^21 clocks */
#define TCR_FIE		0x00800000	/* FIT Interrupt Enable */
#define TCR_ARE		0x00400000	/* Auto Reload Enable */

#ifdef CONFIG_E500
#define TCR_GET_WP(tcr)  ((((tcr) & 0xC0000000) >> 30) | \
			      (((tcr) & 0x1E0000) >> 15))
#else
#define TCR_GET_WP(tcr)  (((tcr) & 0xC0000000) >> 30)
#endif

/* Bit definitions for the TSR. */
#define TSR_ENW		0x80000000	/* Enable Next Watchdog */
#define TSR_WIS		0x40000000	/* WDT Interrupt Status */
#define TSR_WRS(x)	(((x)&0x3)<<28)	/* WDT Reset Status */
#define WRS_NONE	0		/* No WDT reset occurred */
#define WRS_CORE	1		/* WDT forced core reset */
#define WRS_CHIP	2		/* WDT forced chip reset */
#define WRS_SYSTEM	3		/* WDT forced system reset */
#define TSR_PIS		0x08000000	/* PIT Interrupt Status */
#define TSR_DIS		TSR_PIS		/* DEC Interrupt Status */
#define TSR_FIS		0x04000000	/* FIT Interrupt Status */

/* Bit definitions for the DCCR. */
#define DCCR_NOCACHE	0		/* Noncacheable */
#define DCCR_CACHE	1		/* Cacheable */

/* Bit definitions for DCWR. */
#define DCWR_COPY	0		/* Copy-back */
#define DCWR_WRITE	1		/* Write-through */

/* Bit definitions for ICCR. */
#define ICCR_NOCACHE	0		/* Noncacheable */
#define ICCR_CACHE	1		/* Cacheable */

/* Bit definitions for L1CSR0. */
#define L1CSR0_CPE	0x00010000	/* Data Cache Parity Enable */
#define L1CSR0_CUL	0x00000400	/* Data Cache Unable to Lock */
#define L1CSR0_CLFC	0x00000100	/* Cache Lock Bits Flash Clear */
#define L1CSR0_DCFI	0x00000002	/* Data Cache Flash Invalidate */
#define L1CSR0_CFI	0x00000002	/* Cache Flash Invalidate */
#define L1CSR0_DCE	0x00000001	/* Data Cache Enable */

/* Bit definitions for L1CSR1. */
#define L1CSR1_CPE	0x00010000	/* Instruction Cache Parity Enable */
#define L1CSR1_ICLFR	0x00000100	/* Instr Cache Lock Bits Flash Reset */
#define L1CSR1_ICFI	0x00000002	/* Instr Cache Flash Invalidate */
#define L1CSR1_ICE	0x00000001	/* Instr Cache Enable */

/* Bit definitions for L1CSR2. */
#define L1CSR2_DCWS	0x40000000	/* Data Cache write shadow */

/* Bit definitions for BUCSR. */
#define BUCSR_STAC_EN	0x01000000	/* Segment Target Address Cache */
#define BUCSR_LS_EN	0x00400000	/* Link Stack */
#define BUCSR_BBFI	0x00000200	/* Branch Buffer flash invalidate */
#define BUCSR_BPEN	0x00000001	/* Branch prediction enable */
#define BUCSR_INIT	(BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)

/* Bit definitions for L2CSR0. */
#define L2CSR0_L2E	0x80000000	/* L2 Cache Enable */
#define L2CSR0_L2PE	0x40000000	/* L2 Cache Parity/ECC Enable */
#define L2CSR0_L2WP	0x1c000000	/* L2 I/D Way Partioning */
#define L2CSR0_L2CM	0x03000000	/* L2 Cache Coherency Mode */
#define L2CSR0_L2FI	0x00200000	/* L2 Cache Flash Invalidate */
#define L2CSR0_L2IO	0x00100000	/* L2 Cache Instruction Only */
#define L2CSR0_L2DO	0x00010000	/* L2 Cache Data Only */
#define L2CSR0_L2REP	0x00003000	/* L2 Line Replacement Algo */
#define L2CSR0_L2FL	0x00000800	/* L2 Cache Flush */
#define L2CSR0_L2LFC	0x00000400	/* L2 Cache Lock Flash Clear */
#define L2CSR0_L2LOA	0x00000080	/* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO	0x00000020	/* L2 Cache Lock Overflow */

/* Bit definitions for SGR. */
#define SGR_NORMAL	0		/* Speculative fetching allowed. */
#define SGR_GUARDED	1		/* Speculative fetching disallowed. */

/* Bit definitions for EPCR */
#define SPRN_EPCR_EXTGS		0x80000000	/* External Input interrupt
						 * directed to Guest state */
#define SPRN_EPCR_DTLBGS	0x40000000	/* Data TLB Error interrupt
						 * directed to guest state */
#define SPRN_EPCR_ITLBGS	0x20000000	/* Instr. TLB error interrupt
						 * directed to guest state */
#define SPRN_EPCR_DSIGS		0x10000000	/* Data Storage interrupt
						 * directed to guest state */
#define SPRN_EPCR_ISIGS		0x08000000	/* Instr. Storage interrupt
						 * directed to guest state */
#define SPRN_EPCR_DUVD		0x04000000	/* Disable Hypervisor Debug */
#define SPRN_EPCR_ICM		0x02000000	/* Interrupt computation mode
						 * (copied to MSR:CM on intr) */
#define SPRN_EPCR_GICM		0x01000000	/* Guest Interrupt Comp. mode */
#define SPRN_EPCR_DGTMI		0x00800000	/* Disable TLB Guest Management
						 * instructions */
#define SPRN_EPCR_DMIUH		0x00400000	/* Disable MAS Interrupt updates
						 * for hypervisor */

/* Bit definitions for EPLC/EPSC */
#define EPC_EPR		0x80000000 /* 1 = user, 0 = kernel */
#define EPC_EPR_SHIFT	31
#define EPC_EAS		0x40000000 /* Address Space */
#define EPC_EAS_SHIFT	30
#define EPC_EGS		0x20000000 /* 1 = guest, 0 = hypervisor */
#define EPC_EGS_SHIFT	29
#define EPC_ELPID	0x00ff0000
#define EPC_ELPID_SHIFT	16
#define EPC_EPID	0x00003fff
#define EPC_EPID_SHIFT	0

/* Some 476 specific registers */
#define SPRN_SSPCR		830
#define SPRN_USPCR		831
#define SPRN_ISPCR		829
#define SPRN_MMUBE0		820
#define MMUBE0_IBE0_SHIFT	24
#define MMUBE0_IBE1_SHIFT	16
#define MMUBE0_IBE2_SHIFT	8
#define MMUBE0_VBE0		0x00000004
#define MMUBE0_VBE1		0x00000002
#define MMUBE0_VBE2		0x00000001
#define SPRN_MMUBE1		821
#define MMUBE1_IBE3_SHIFT	24
#define MMUBE1_IBE4_SHIFT	16
#define MMUBE1_IBE5_SHIFT	8
#define MMUBE1_VBE3		0x00000004
#define MMUBE1_VBE4		0x00000002
#define MMUBE1_VBE5		0x00000001

#define TMRN_TMCFG0      16	/* Thread Management Configuration Register 0 */
#define TMRN_TMCFG0_NPRIBITS       0x003f0000 /* Bits of thread priority */
#define TMRN_TMCFG0_NPRIBITS_SHIFT 16
#define TMRN_TMCFG0_NATHRD         0x00003f00 /* Number of active threads */
#define TMRN_TMCFG0_NATHRD_SHIFT   8
#define TMRN_TMCFG0_NTHRD          0x0000003f /* Number of threads */
#define TMRN_IMSR0	0x120	/* Initial MSR Register 0 (e6500) */
#define TMRN_IMSR1	0x121	/* Initial MSR Register 1 (e6500) */
#define TMRN_INIA0	0x140	/* Next Instruction Address Register 0 */
#define TMRN_INIA1	0x141	/* Next Instruction Address Register 1 */
#define SPRN_TENSR	0x1b5	/* Thread Enable Status Register */
#define SPRN_TENS	0x1b6	/* Thread Enable Set Register */
#define SPRN_TENC	0x1b7	/* Thread Enable Clear Register */

#define TEN_THREAD(x)	(1 << (x))

#ifndef __ASSEMBLY__
#define mftmr(rn)	({unsigned long rval; \
			asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
#define mttmr(rn, v)	asm volatile(MTTMR(rn, %0) : \
				     : "r" ((unsigned long)(v)) \
				     : "memory")

extern unsigned long global_dbcr0[];

#endif /* !__ASSEMBLY__ */

#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
#endif /* __KERNEL__ */

OHA YOOOO
����JFIF��� ( %!1!%)+...383-7(-.+  ---+--------------------+-----7------+-7-----+---++����"����M!1AQaq�"2���Rr��#3Bb�s����CSc��$4���D���TdE������'1!AQ"2q�a���� ?�Z�L�[�����=D�6]�T mѰx$�6��@ۣ`�Itl �"��(6�Dst�2:��Fk���x���4��K�h}�l �?r��@��!�Q��Y��?��-� =��O�����(6����<A�x%B��<A�x%B��<(6�@��.���*%���$e�m��T�wi��~H�]F�Ѱx"�`�Ul��ꃁ���RPl�6�UIA�x(���#�B��zy%�<�L���mvN �ԭ6�Y$Qk �S��䮰�K6ף�x�+�T��L4���>�C=j�������p�|J�ǥ���b=���Y�6g9��F1��Y�vݩ�`��塏��>� � �ݨ,�����A�o�=W*���"��>����� \ �"݄(꧈�y���9�m���d�aAD�u&�T��D �@$BITU�"��D�D!BH�� � �UTu� �^c�?�[ND�K�`�\F'�jf��<�G�G��B�q]�����!tl�6�]\4mѰx"��<�6��B�֊�o4.�Ah�8QM,�y�����%cLh��y�c����!�8Tb���h�!p�q�t����EIA�x'Pl �KT N h6�J�P7�6Ԩ�6恰&��� �� � ����R���)m�`8�nC�J���E��%H� D�"T �n��W�s+���x���+g�?t��@�����;�>�o��0�����|Ћ0�����|"�J�%EBBBB!X�����|��X��̟s��Ӭ��H獎ŏ m׷�0���—���2q����s�'q]�����7�%����hp8EAYy�Ӗc��9%�A� _g�ٙ���}ӯ�Ul�Ƽl Ѓ�a�ۮ9�i�*��R"�*������:��j�zE+�H ����kB�2�e��~��Zd# ��0Vr�T�ev������Y�����-8]o��x�~)�9��}W:RF֟��P�A�� ���G+hH�P6�����:���Ԁ��I�O{Y�F��$U"H�#2��*J����L��L�B�*��T`���(�-:�R�H Z��"�B�Ihh��B�B�����urP�%� ��9��7v",�!�A�b�X�V6F��� ���^K�+��f��qm^��'�9�K� �����o��! ��P�%B����E��}Xo�U��(BXJ󥯢t��u�&�}Xj +%�7+�c� �\��t�9t p*)��L�Z��T��KTC�NGT�PH pQ�� ɚ^qB ��8!�*��� P��"T iHS���n��W�s+���x���,mtG��@��D~���� } tY������Y���4����!!@!@!@!@�a�^h��R���*��|!���Us;����n:��#���4-h�chW꼝���%�+Z�kA��E%��4“M$�����@y�q˓��ʽ�� $U��������eH�-;�a�ކ�&����*IB� �Z�w��;c��|�3JZ@��-��w�k������Q�Ϊ �g�d���I��G����8�N�G�����(R)�2�_�]3;]z7]�2�w�r����I�Iĭ=15���b~ 2�{cuO�'෎V�nyI)��1s�� ����i�lT*�ݠ�������H��p��^j�C�Q�B*(������(m�Wb ���Z�)P*D$EGimZU�ViZ��┵\�P�L���IW���Eh����[榚V�R8+l��zV<�B�M�j�V�pw�%�*�UKYǒ}�J�% ���(�����HM��NQ�S�toԝ�ܪZd�ল���,UP�J�=�Z m�T��-]��y��*k+���:�%J��V���X�i�o6�D38�h�=� �'G�$�@��X��H�P�~��X��e�Ã�����4���WS��x�3���q�˓V�S��k'�K�w�N�w�eb��,��bcw�1�� �ȃ�%����͖��Bd�J��*V�Y��.;Kh�� �*���1 X���-�� �OJ��$ sCU��H�Zj���N��e�m�zT�"T��%���8�(Q�4 雐��d8���j�$NH�'$@�� �a�< ᴖ��K��W ��5}��{��-�����w�}�,Y����䴣�,��S�|�R��BT D!�R ^��I *I4m%Gk�2&�y�m$�k;�7m��sW���:�q��!汖s��]�i�;(��ƣ�7_�Ve�o\㛜K�y���T/.yܝ�2! �AB(BD��ꦽ� �EX�w2��\�����^{Nɥ�=����lB�V���y ��t||�K$�v��Ȃ>* D��Q��z$�y��F�MqD��(���鍵M2 �G� ;[r*4�T�Rd�oV#�t+���P�A-��v�*�>��PhU ���-QJ��Y�mE;k�"�F�?%���R��&������G�ӳhx;�i��h���5��+�Cr��8���B�:�+BI�Ϯ�LOٳ��=�~��,��b�t�C�6p\����x ��«�!{�ҽhh��7<� ĊW���<�CNw�ai�@��ںf����j#^�Ny���\^rRU9�1u`�RC% T)SCM��VtR��U溢�f���i�|��Y/SpWF�V ��*�A�5)%T9����'B��O "�TTTQZTm�Dv] �����U����������R�����5�/B^�.�/���"rE�8B)�"�P�D!Km�<W��y�� |�[�m���,Y\A�]��7��f����ѻ,H�Zj[���eh� (N+P�U"N�*���ء6L� 뛐�������"T D!BBT�"�#��I~%�͑�W ���Q���w��] ���.���.��<���O��Zl�,��S�|���%F��9"H�Cj�66��4Wy��NTR��i Y��� '����|���c<�fژ��E�����\>.�|hH�Yem��&��"h!!*lehjӼ �s�HQ�b���� pi�Η|h�'�Rh��SP3 ۽�$0��P X?�w�-;5���4h�{� ���/U�v ���ְ\2o��e�����@(��+�u���Ē�����B^��&�M]�B� �"��D��@!@!@!,�lΖF��W=���^����da�cehi�����_��#d��[ 9_=�]�Ù^�$!�-p8�u�(B�/� ��A�!�����\�F4q��3����:�[�>�w�ك�[���]��<��[�3�'��M+�yMH�R D�P��(�P��AJ�b Qq�F�bq�ߪ:J�$j��8�-5 ��z@�#��K� ڕ�N ԺKړ�^y߉�Ԭ.�tv��n9��w���n�|s�Z��;q"{���9�! �BJ��BMe��=�`���֍�&�Ba�{� ���v ���@�> ���lp�6������uRh�"�i�,ɯ�79o�*�� ��V�&�[\v��:�bq k�|���\͒��1��]q��C �xi")��*0w��{��0�c��������߸ɢj�X�MQ����Y�R%B�D�P��!�$@$J��J��K�����r^�V~�� p�KWg���.��m 뛶���L�Z Bã� U; �H7�V�A��+�B��r R7!�%\���!�!�!�� �a��W�����+��Z�cw���]�C�D��}˽��]��g���>KM���?���� G�4HI&����i=,�Ge��*��o���ׯ r�c�RZ����$� ����fӿ.:��q'\j�M\㼕j�g�߃rh�� � S\ ��g���d%UkY� ��?Nn>�Y$ &�,�[/I�ZC��>�a��S�K��p ��� �Ƭ�QY�X��h!M�m�h�8]p���y%� C/gt����ڭX��� c�iW\�;'�i�� �atd���ā�7(6L`��]�=��hP��.�ss��X�9�X��ji�;��t��\��V���0f�87�U�?k��ww3W�|��=L@� ���OG��bv�Z���uj��AD�BEjubӨ&����F�Wgb�G���:�uT1��ni���y|�X�Etu������n�k�D��q57���g�A�n ��X]&����+����sD%�0�p��<��Vtm�����Z���9�^�Y*�(�{�/��j���sn}uz�����_n����������MErjΎ��[#N-5�5�a\��cu]m��M�WN�b�_ p�t�q�~ '��H�- y�@7%Oj�h�y/B��d�k�-{o�,-5��i�4toWx꘳�_�(E�LJ�í�m;�]t��V�^23I�{�h�g�43-zJ�ֽ��g�Z "'!N��:� N������Qku�8�3�n^���s,�6(� �nv��.�),��eƷK�\K����IPO�A��������e�K���ڌ6����yW�)֋��Z}�m{쾙��x���{hyn+/EY�l�W!-�$�U.��I��� ��� �� �/M�;��Pݎx�"~+��Ή1�&ѯ���=����#�ыv�$�[�"�R��To�v~)�U�˨ x0^q��S���^�d����ʠ�W� ��5�B���dy"��&�õ���c��g�+��9��ugh�ޖG���7������ �곗Hz;f�L��`8���{"��؛f�1��&�)J[�I������!n��v��b�Ik{�������ŋ���qo�s\��}ɛ\*KO<=h�L�2�U��Z� ���v���[O��8�@7$t����4S2r�ʬm���)18op�?��]1%�<��&71�k�.�s$.?-��s�ïZ� C�DjFC�w֠r+�@U4U��xY2����N�w�S�\S+�� P�0D��� ����R�>*D�3�֎m�Fu��v^k��,�9�-�V����M�k���Rw֏�Z�[Y�=���q:Aů%�>�����O�0�pmӅC�^뇍6��+E��N�f>29^L����=e�gi�-0�����e�W5��U�E�x�і��(ZKH�F(�Y�mrA;Gf\�H�z�G��iw� �^�r�y������-.��9��2|�%���ÌR�����J��� x��ab��KD�꾏!�k��D�s4o���F/9�2��fv��?y���z;WLC�T�*���l�"�b[�qi��A� ����Vf�җ�W'fA������� ¢�#h?%.�҆�lߊ�_��w� 6�uA�*V�;M�y�*�OY����1MZ6��g1�PsWiv�e���%B����@�B"�@$�TQF�т@p�q֫9��+��F��bF� VljWx�B�%���L����ۗ$��˒r������ � � d�p:KZ����+��Z�c{��r��D�ކ}˿h}��"be�I !���-[��n�{ft�J`�ь7f#�\c�{rڱ����T0уQ~���Q��h�����9���;��Ֆr�Ts�Y�dt��L�ٳx�R�i�<�B�g�=��^caؤs�EI��SAEɤ6�\��b�pn_�Z�U�u�� c\}Z�a��y��B�PZ���'�Ya���Ʈ��N�� ��I�C��,Vp��+A^Y,��,h*��[P�!�|�����I-,nn��& �x��u )�T�o��%��]8-x�m�dh́�sz]�/�#�}�{� �uq*͚��1=��g27�4�l�;���Rn�v�G�zܑ`�Z9���j� �ᲈ�X̜�]�$���OYɊT��2� %BAJ����� �:�uԮU�j_� z'�48d�T'��F�g�rI�Ƹ��+ :��p� '$涨�䳶J5�k�48Tk�[;c��K=��zՕXʛuS��"��Q�8l �m��ˋ��k+���ᴇ��$V _�%$g��k��]��GZ�t�^ʹ�쮣��k��m�2V:9׊8c෎v%�8O�&}�����]�\�G4?��3F ,�6I9�k��^�����m���TЕm � J�P� ��}�� ��Y���2��}�&���{��|(Y�o���J���v�qܶ��EAA����BG�o<�Y1�K+�����۽���^�dŹ���-�v�����P��It���sh�VŦ���ޫ.H�4+�9m�ώ�Q �H���%D�@�!@�%@AFkK��B�&hCm��8'&7.A9y�P�$J�B�P�*BJp< �t���͑�W�����E- ��#�h�8��� {K�s���Zgu���m=IU�v���;!�cϴ� ��J�"r\ 0 p��+�8T��e]ĵy�rߧ\'�4s\�ep����� <�ޑ}ƶ!��9�V�Mk]R;1���4L���'2j���B��F@c���f���e=�k�t�n�?X��2W����j����&��Ꜩ�n�WԮ�5� �����G���|h�m�(ݹ��@Z��VY$?�6�qy$�'���l�z��Õ��I���pK_ny�Tlq��<��.#��)��&���0�)#;s�`k��xn5ʞ�4�-�Y� ���'�kFe���k%������=�{c9���u�L�Ut��,�`g���iS)Z��Z@���l8B��P1�y��Z�ѩ�\�㏲Vk���&K,��I4����iX!��U,���7‰l����`t��E�I��ʺN�P�(����k!�}֒�\q��-m'%؝CBh����aTn[�%Z}�C��0P>bs$�)�4���x��9E�&�^EQf��!�mt�z��8��ձhR�Rw�ͨ��{>g��(��c�C���p�� �޺ S��n� l���$lgn�ۂ����I�{݉$�XnM��-{��Z��E-����n��*Si/`s?%��8��6�<����� \7A��WZR#���Ǔi�˹ V2*��B�� �� T�=3n�&юA�� ���%��_O� ->���G�EgJ�C��a?��tl@����6��m��Q���p�s(^���*�� � �Tfi :�b��Ed���׀�|c���8^a���F�[J�~7*@n�3��2��j��mik^��NyF�J�g�������6���*@��Pg�珢�C�g��*=5���R��g�=U_��;G�~)&��M���\<�F,�]�&��<\o�L�]����g �� r޿��������$kk��i(�!�ݥE�V�E�;ͨ���헮�����5���TiTM�z��+N����Ī��J�e{ݺ6 �n$�q<�Y�!�1�yAs����.�@��U�%+�έ��u\]J�`�Mdփ��C���;3��:&�^��7NK ���øS��]��'�7v�M;�ä\BD�1�P:�J#i��u��e���mZ���<���X?eew'8��� �=��փ��.����Ԯe�c�e�O)�KZ9 rW,�����a#[���U[�03\ޚ�\QU�3���L<⵶Zv�dP2���4d5����\f���f�b���н�~��x��e�I��J��e�M2���d��oݴ���\|2M��6U�.��RYt|���O~�Q��pV���։c��C����E:�9��q@��N�D�;� �y�;M�Z�3���BԷڒ� ���Sm>�t��q�O@��=��s�6����H���EAi����e��;��ղ� p�<1T�&��79�ǽ�1#�5��'xµ��eODB��Z^;@7o5���"����xZ+�!S6�<�&�5��z���xa�.������73k�6��Yc@@ � ���D� ��� �f����438D75�/?��.�%����� � ?�7�L�)�u�����ٙ�S�]��s+���?��r.�G��e���sBBB!Y�4]��) G���g OҴʡi�͐�6QԼ�' �2wT�~��p嬙�z�q��ˆ8a�-��f^ˆҀ���L����E4�GX^�5�(�R�a���>���F�v"! �5�~>�]�,�~*2��n�M���>�i�A �B1U����<�R&��ϊz2�*FV�ѵ����Fm������Z5���~�r�T-�=� �1�7���pP��N �otg���dǟGo޶D�l�U����T��hp8��ε���n#ӊ�[y98��(�N!![p5 P�D! �� $8��r�#r�/;� �ȪD rTԨ�J��f�y��i.w�#�n ��k��V���#�b7]���|�^l61�w�ܼO�\�=�:`��s:=3��H��zJ3ʾJ*�Ղ�f����V�8�c0�pV[�u�!5��*ZRJFw�|�(�Ù���{���5$�8p �d$�A�J��rI���4��Gm������V�2����#2��Y N ��C��zy���+e-���q��H�]<�9�W{��%&��g��2���[���sq �U���f�Ӎ�<.���@�e=�$h�y��r��� ��vޢ���1���{.�%E�I�6�����L,��s���F�e`�Z�w5�� ��?� ���uzR��0U��?́o�i#���t��)�u[#�{M�9�q��劘�?�OdqOџv8���q>�}�c��Y�:E��U��tj/�i��#�7�yQl�����4��vUg�~;�h�� �@'�\�09�9���S�Z�Ӕ�K]��KE�8�l{�?V��ܪ��{ւ�ٱ�ԕ��zd�U�tD��~�*.j��[Du0=��w'�kR�q��z5 x: Dߘ���k��WYh�Y�OUg ���t�w*�>u��du�L'P�����O%���iuմ���=�JpvnZcm�^��OٱC%܌�`�����Ee�L�u���غ�^�owȭ�<2�����W���v�����[�KK_P*�_i�ͮ\A�Fl��h ŭ��K��r�E��;FB�qSUs�'�W�'v�ߴp?tës��`�bm;b��H�bN���q�A���u���ki�Ԕ4A�J���"Ƌ��36C[�sLM�k���⺖��/����z�(J+{���+�|��8Q��\����͎���g��ޫ#-s\�F@�d��CR��4;��Y,⍾[4m�1��m�>��4�9B�� .�%�WTm�w�����Z։n��+�vD! :�ZO��7����t�.�\����u0 x��K>Et61�g$�B�!@!@!T ���%�̭/ ��]Ȁy+)IF>�����Ů����;�+Y�p��xzqY�3��!r|�L����͛��O�ތ�G�{��snV/9���v{Cd˲�~JE�*T�Q����[�G���z?{� �T��pg�H�;��ϊzBHP�m�6��`�>�n>��V�G� qEh��S� ��h�rZ߭�ю+$g�� ����xU:3�4��M{�f���^'�ܰ�}�7�y$�u�V��R�s@z�Z05��4d�i�&�Эe-��6�5���]�v�a# %dU']\|��vv���~����TuN`u ��I�gn'������C\#�|j�>�t��"�3�� ��$��̈́��1��K�yƤ��;�'⦉�A ��4�B1*�J���ft{I}fɓ�� �n��n!>ۦ!���\�n�i��& �s���+>]%yŐ]�����G�8f(�m,v6�{s=� `�8:�`�G�;�à����6��`��?S(V�"6觼}��WW�lQ�p��J�l�ST]��0V��LX?��j�,��ԝc}��O�;C�)�v���,toe/�Ԩ�D��hhFí] K&��H륎l�b�+'�.��Hޛl�> j�c�woI�����`+�Jݶ�D���z'S�÷/�r�_�[A�i��7v��w/��@ ~��T�pɼ� ^�)�z34��$D ��R=�l�[�j�a��FGT&�ŧ6��V��H�S�ttY]%o�3��y O�Y�4ⴹ�����D��F���94�zx���]{ܾ+7��*;P�nX�E I7t�XW���4�KD��i���epS��B72U{)B3cZ`nc;����բ��F�<�72Bמ������\k��F��?��$-�F�� ��Z,�fHۯhsM*�4��FY��@цbP�\�ÎW:s@JE�.�������b��N�D�$d��w�]49oi��Z|Ŏu���+}�WC�6b| Ǵ�P[��ps��Q��`�����=�G6�c� �R]N&�&�Fƣ������u�� i�Yњ[�������n���eu� ~,�=�k�4d��Bז�������;���Q�˴Ѱ1����()�yT}4�5�pd&�i5��n�ZvN������eÔ�br�~^�6�����v�m���:���Q=�8���O���Pw8��汴gL,Ґ�(�]{K��<�G�����+,o��3^�暃]��j �E �i#;�Դ v�iz3ƃ� Ap&X.Iڤч~�vNBAMy�uf [��u@�v��3�5��$�V���5�����9��i?�72:ր7U����S~�"y$��Rv�C�+�5�NЋh������ �mt�+�4��*$Ұ!�1�����z��:*��3�l�sX�1���h�J�g��`{NTj#h#Q���yL�y�ڜ1,}d��h�qh�p�Eq��g,�f�����(���]'�E]�����S?y���O��G˽G� ��?�͓�$�Ew�4{���I�i=��o#�Ը�(��Ru��[�L�ܾ݉���e��������_�g��?�\oY������U�}'����A� ��������DU�e�����M�o��/.S��o�aVsd��H��a�2v8�����V琽셤� .q�"m/P�$����u/i���V�;��:���­�2��W��.�{uÖ����>���ô1���'2w�i L2 �W(�}d�9����� H�A�= �!�) �d�\D�������ԥ�f���j F�AA�p 䴖u�G��XHd����L����xb7�Ly5�X�����׳�G������a�����4���t9=KjIµ+���c�x7�Q���ߊ�!T*��� :ߣ��nb)�h+E�����̓�k�k��+MU�X� ���=�Л�Է&����ݽ����;��]��Xwj:���b��C�Z�i�>9��sRf��h����� ��y�NF��%Mn\���*TԵD*Tڥ@�SP��SR�Ir< ാ��=���|��$��\&����ʟ� ���].=�������ĴsX���U�6�����*�]q�T���s�]¾�%��> Ș������غ�C)[�x$���WL�(,P�6�m�� mķ�5��MJ`QU����3A��k�W�6 ��� �����p8��5�G��ߑ�8�8�㹠rZ�hm nM��\�/��R�D�45�Z(� 70�B��Ktu�/=uƨ�:n;�y[�)�4���Hʂ6�[yƙō?�4��P��;��Ini���l�CJ��_I��j�,m��A�)N ;o�?�o�+�ש���BQ]t�i�h�RQKu!��j.�HIu�D�W�'�EٴT�il�}YV�>�{[��������uV?Gض���.>�Ol�/�+�݌@�;� ��Kr#��yͮ N��R��b�4��f�+�N�������q���๮��'Z�hid/-m�/�����y+)���4��,�X��p0dC^��A��jk�h�|.��6݆�lu2?T��р�55�MJ�3lWL]U���C�g ��o �W���~���˯P�@H��H�۲�(rjD��OE��E�����˻L�9r��J�q�����hΝ?�b�)9�%2��׍k�(��p��D��l��8„�m 3�J�U��b���� 鵝��C+����p��;���Ŧ��L�J�6��VF���_�U�z���ϴ���I�U��"�������.�@f�I��f��8�R.��i��6�X�V���Ү�Yg�u&GK,.oU#X�H܉qp7{�h����@)�$����j���`�I��5�lQ����⊪�y f� �CҤJ��!%�\��o�:#�V�DkpVI=���h9�n�� ˾�gcm20�����u�p�kȯSj���姫�z�N �և�K�lg}�a�ⴴ��8_#�Ɨ8�h�y�EzGz�#d�Z]V{��o1�6�2;nG�4� ��[�Ⴐ����$�W1�� cƾEJ��'��S��[��Z�(i=��j�skq����1�mOF�,� �h�ܕ��0��1�P�v�a��6�N��ӆI���Ln�1�1���滑�x�l�x7�v���y���X���-�)���W�]�uN�P� � ��y�(U� a���m h&k�����(������gk� �1��M(]��7�v� �xi�K,a„,y"������j��<6V���Wm�' �c[]N ����@ܹ'U1���R��@�SR�T$�J�� &G�\5�}��� �Z�w�O�yfy��7�\O�\�n���=��(�.��v�OK��:�����2Q�q�� x�.ӦhC��=IU�ƙ��h��' �)��R��E�g��cuG!�i�}X� [K*����+�m+���F-=a�H難�����5� �p�U\���fd��#��Nh!fݪT׶�*" adL����edr8��߼�d��PKt�{\ ^�{.i��P��$l)�[�Ǎi�j�Y���8 5>��e�p'�D,8G����C������Ň�5ql���+u � ����Tv7�`;FK�� c��Tƫ�zQ�>�3�;���1�V��N>R�Ň�G'/�?�ƚZ�ˍI$�IQT�NB�2>m�6�o�K��rU�!��Ev�BiT�"�BH� � \ڧ!w2�VSKVt�D��k��p$�L��F�<QoG�� �����׍�9�Ts^���̞&L��Esx5��4�E�0�����VX�u~6�t<��sṷ~�t����O ������xR����Ů�\��Qk��� �'<��jpx���Go��R\�S.���Ë�ӯ#�: ���~�0'���t��ׁtsK��hd��4����=���^��{Z����i�EAS<|j㗔Q�E� �� b4���<��-KL�_��J6юÛoj�\�b�2m�9��Y��G�_������m�/�B����lo�H�aR93�o �=����Y#|�IBZ�h�c�5�a����sՈek���F �*N��$`sH ��2 �U7���?w+��:�!�t\�p�CP]x��c(�A)��Sj��qm> ���0:�c\�=��|����V��1�Q� ��j:�1 9c*�tx:�i�hAe p"��i��k�T�no�;�)Ri�w��WF�upJ��@�SR�pB@��6�j�R�Bˑ�W�WHv����o�v�8�uO��G`W3W.7����}:q�i=*�GĀ�,�7%(6��I�ݓ����xM�`8)����$��$�WfY,���64��4h�����^;(u$��^rf�ơ�3䎉�u�V_xg��9����N�р��ʐ59Q���4V[�4��M��X�L� 4纥5J� ����k�r4vdh����O*U�"�!����3C$�"��+G㌟6�G  �����Yt�Վ��2sN���ɉq�@#.�暁#?)��j5)[°�S1I��#��p�C�KKi#��'ǵ�^���/��LK[�7� �s�9�;ҭ�J���x�J)^�U�{'��EI����T4T�}�k�+ �~#��{j=�ﭑ��t�����\�A�/g�;���k��O��V��훧-Ή�k0|��� s����y.|G��W8���<έ�-��BKc�e�;��[_�+%g'���o��i�*V�@�#�TM��Ց�9��6��w ���ed��R l�N��M�)J������G�V�L�k?UQPK�#��(�/F᳓!d��dpȜ(���n��E���t� qX�"��Y#��t�}�`��v����FY�=҂ )`4|���]��xS. ȥr��ZFI�t�>�ƍMh��%{x0���͗� P�B�� � JS$U*B ���@!@!@!@QB!6��� ��-ςVM/F�µ��A�� �4�,�Yt�}k���X��6^�P�{��ӆV�&��u�F�v�Qmtg���g0��-.0�ݺ���jk��{�'j���H�W=�{��8ԯ.vd�$�Ҭkݺ%-ls�����|�Яn�A����dx9�g�x�Y��Ln$���)Z�sV4�cO�Y�F<~G��b��~�?� ���m%��w�џvH�)��bgH��,��f�%��B^�}��O�o�)��ү�����e�}۟Խ���.�c�$p������H�׆��u���5�x K#��.��P��i�vG0y4+��~�?�<1߳�O�~��-k�^�!|lq���q�HJZ�AT/S�Np�UgDXoG��E>;Q�y;_=�Xsy��C!��a�v�u��'9���k8v9�#��n���4 qћ���q x�nz��|���b�,�i�� ����x�we��R�EB!@$)Rn������z�x�F�-�pBF�8%E BD� �J��J��9%�<���.�Uͅ��Y)Y�$��j���b�7=�;qB���y�o �u�sV�^���qǷZF�t@�}nA�D�� ��!�k����6�C!Ƅސ���c��$/b� ֆ�ZA�P�t�yS��!e��!�!�!�!U )a�s($��7�sc�+�+��W�6y��Z�s]�k�k��P��Nٺ�[� ������zZ��X�PZ?) ��;u�\_K#w�~8�N�+A»n��lQ�]��$���]�IIC��#�kN ^�����C�<�i36���~ � ͺ?�Y�չ$o�� �Ů����^�����@ � �ZG�S�a��� m k�w �0�AA)�Ǔ,z�8�&�>��V0�Ƶw�ܵ����(7%U��-%��c�l�u�C{��&Yܻ^L�f���sZ֊�8�� 䬷[m���O�i�?x�\�L�g.{�+��1���\Ʀ�@ i�NB�s ��龝F�Yfi�� )���Cy\���\d��{��s�4��O*�N⤞�u�j.uMv⚄/���|ܮ�P�*���R � �!P$J���PMN@!*D��� �!%�D"��}��:�f�R��E�z�х�}RFS+�w1�� �x/7�O[v��^�������J�).���`����Hm�ROz'1���0�\���S٧��Q��g?W��ub{i��]ą��Ykhu�����c}���]|�*�'��ix�϶h|�*7�����!|��X�<2��H�g��k���=����8��4k1[v C/N���{Z p�ؘ�Mݧk�-��4������9B�v��y9r�^ɡt�v������4�� �V�^S�+��z�:��\�.�w�1�}X�ö���j�3ӿ��t��O!�_��C����&]����o��4 �����+���ľ�&Jw�X> �KO"��`��V �n=�a\{k?�UT�8%_F>aP�"�R ��@���P �P�B (Q�)�Oc��ÁBi ��� � � T!�R �F4�՟ q!����MN �w"|��Jr��j�7Wol�����C���R���1����[�x�B$?_����c�*n���i�W��������/(�ұ���ͻ#���q�H�� �L��V��u��/�^Ž8�Q���s�t���Zߎ�&�������y5ɖ�eA�f�7B� Y'xP�CBq`��C0ƻT�{��G�,�M� �B �#%�=�_Z��l��6<;�W�^$һߣM'G>�Nl~�x��T�5�z*AN ��Q�v~*D( d�ge���:³J��Pv&�\ ��j�F��4ێ��;A�9;楆F����ӟ-�{��-Mk@� ��*]�n��+ pp�MB�L��x�ɻ��Tdؾ���d���Fv�T��*;BBBD T!UҖ��3kG�L<胗^.q�r��^7��Wkh�3SX����U��v���7K�8��}h�̖��=K7G<�%���KJ������}^�T��/����d�c�f�*rBBBBB ��A�zF� �HBT �zi�ʗZ"���ƽkxH�v�? �C��%y�Mz1�8�aoٻ�h~ONƹ;$�^#�u�6!5��^���O�W1�.�]7F�`H��bw��\�GԮ�ݛ�p��]"�x{.�o�� �R5�S�i���څo��+��X;���Z2�M�*����FѬs^�l��9㓼�P����9���*E��cHQ�k�f�ٸs�Ժe���� ���\/N����>n?%��t���3��ަ-������´TV��1ߕ�� �=����؎ �(��} z|�T! �BD��E�4�d�\��T�R%Z@�!�* p�@�P� ���f��HF�/ԦM�&���! P"���T�A�У�g?����5^ �m� ��w#�����ndδ>9�m�����Ƹm����{z�o�;E�G��ݐ�g�>��`^Ch��^9�I�q>k��}%2��;Ee��q �i�� Y��8Uk� {g�=�2Q�pAM��Gխl|26X��y�8�TsUKT���z3�Yl��E�4�FV�]��A�~J�{��Od`9����}�q#kA����su��{.���Nװ�5��#"4\,Ӵ�qb9�=hZ� hv]�k�5���0�x�հ�+)2 R!C,�vNН��Ɂ��G��J�#� ���5�-f�=��{l�o`EA�*�2^��S�e� ��8!W6��4a��#��%Mn\���P�*)P�*D U��Ii`�I94�>M�Z�����6�k$y�KCԳ��5gl��dv�s$���W�~3�B?t���xooL�WC�z�tm���>�;G�i�z��}��M,�}�a���S��5�M q�:r�`!@!@!@!@!@!@!@��E�8q'!�=2��՝���Լ�=K���:�e�aX�A�489�c�j����^����EA0B��t}�I/�������a����<�r�9-6j�:��������+9�,"�� �������D������F{�=������t���P>�s=�?�Wn ����1�;T�Ŵ���j3�8|v��E����OS�Z�� �����-i�p��׆֓Q�Nn?/qǃ��껅���m� ��.�9�p �dAȮ?���B��0��ג=�L�6X�G.���Uev���$v����U/N]�:�T�uB�8_O��g�B�*D�6L�`��Dȃ.k?*�*D-!P� � D�F D�(���P��b�:��KI����#��+l��TB �B繬cK��5�hĹ�4s)��~��.jt��p �P�MGjPb��;ݹL���Α�&�|Խj���Y/:�/7�`] .��j+�y�^��"�[,���i�fY�s�ye��66��$V��;�W��蟭۠�f��d����R÷�;�X�.�:�����7���p�+�ccs�m ���(��fM�m���[,P0E ��|&)#!���� W"3"���aӯ��~� ����������hk�7�.f����*RK�����ߢ�IK~Z��]- G�TDӫi9�����o�Me�ء�9�Dz�$�8z��`@��k#�2� �^�C��Ѥ:�F�ܤ�� u�E��C������_m H� ��v?�m��W���.���8C��w�q澴��������$�T��Q��D�kFƁ�:E�g���u�GP�����;���yu�at.+�(�0s�y�?���{*G:��*k�E@�Ȃ����47N�J��UƐ�/�i#ۈ9�{��W��~.��Y�](׀施�[MU��Xu��7� B�T!"BD T!!!�Al�2F:7�9��X�qS��V� �m��$�2{.��89������,�������#d�#��]�����"tR �ÛN�4�!p�j7� l���G,&7bЇ��G G�'X�e��e���i9��x��#��D&�G`q�qR�|x+C��L��C�ѵ�7�#�1��:��F�fR�Ni��,�� TҔ��v)-�@�dto&�:��x���5�J�^^^?{�g.櫝R�M,���'b�r�c_?%�&��O]�H�D3R��5�����OBT����P�(�R �f�P�D*�,d�>7�NrUB�'jICِ��63����&��J�QD�J�E�e릊��t��xҍ���ܫU�I},�G >�����äu�Hb���#m���c7�$M &����Y;��دH�9饭���m��fN�/�5�`Z{ з���%�=� _[�u�{�{Ndv����kk�M6�p�'8H�ėd�%K��{F��>��9ͺ�lkh��n�N׹� ��.��h#G��� ��o��j�<ׇ &���0���R�3+�N���� ��4��kE�5~��:��5���A8�k!�c�c���i4�4T8ePuQ3E}� ~���GՏZ޺id��n!ΒS�2�٧|n��D�E#�}6^iY�O$���z�<�L��@VcQ�} t�i;`|U������H ���KC������Z��[\�7������^�����87ch��4��V��mC��y� ����81�������SPv?C�^8-��G Lmc 4k]V����` kj��cm|�2="���Z&��ZZ�� Mpk�ZV��Լ������7n ]�6���]���ˡԢ����.��M ���4{��V9��Z] d�ɥ#'�P Ay��ю�M�2e{#�ѭ܅M7*q���MN�v��I�HsIii����FE\q��諒*�-� f4� �5,�G�ZN׹� v��ql�#���G��=�|�t�q�U�$�¤�P��z7n�Ŗ)+RX���]� �5�;A�\ѕ��RBOݼ=����O����g�y�ˤ�f^�u8X-�fk�Zj�H�j��7��[uSr��]е��6,�M�ё�渐�iZjä�'d�\3�[�{��\���Б ��H���}㸡%�����i��R���U����P R!���?O�H u�[�Ok�C�=nŠ{O`�PO�+WN�YX�a�狍��5�+*|^����?Լ��n���I�v�vC�W�N�wh���u�6�^���H�� �`+UP������B?�+�n!"TFu�:;�*�ԴCxo,�q��&�4���ne>����L릏��#}���g�$�W�d����O�ZkC��;�г��;�dZ�aݶ�J`���=�c0���=��if����oٵ��Ӭs�. �sIk�X�=�0~#X:��q�yG�� Sh�[���u� -5i�GQ�E��вZE�Dq�ym��ਨߗ���+0��d����h:�|��F^�Qg�Ϡc\�a�^k�+�tz����f��U����q+ج�6F۱��h�Ɔ��'�Ayv�o���=��U�Y鹅��U�5��4{\ñ�->}�����##N��8x�sX�x�;��)�鯣�,��+g~�U�-9r!y�����~�>�h$e]��4^�9�qˎ�:l��Lb*�஻s�f,��ZL{Z�-�D%BH�R!*PN�j�)� �,X���D�.m,Œz�褕�[��:6WW$m�P�*U� �Ϊա�DJ,�J�!@�ZU�1VV�J� Hn��=Vq�KUa�*��U��aP�*���iCf��O�M��8��XK٘���S�=��lK��P ����,�ס"U�� �p�r#"3 #�J�>� $��,��ٚ�h!TB :����[���P���! 8"�!�M�T ��@�H�i;A��R���}��|�PaO)|�?Q����;#Оj�A2��kO�T�2�Cv o* �5����=��Axr��N3Qab�v��ඊ�N�����f��q��B��hWV��o��[p�B�U�`�F�YB��#��-4�p޳Ee٥c��ֶ�?j{QKќ����I�t��\e!�`����H�$��J��ؽ���q�.�|~_�˗�c�v�tf�k�b����iFKOgaܷ!���y�`��Nd� ���њe�Q��jy���������' ��|����Ci�T�)�"��PF�U�=��;�pۭ��u A�*2T!!!! �+I��v� �=D�`%$TBH� �񦲵t����K^�#�r;]�w��Y�lk&�Ĝ�㋜w�S�T>8�E�� ���FPIJ��M(�J�PR%B)r� p ��7�*D���;;8�_+}��?G�e�G��_�v(Ve~��}<���^�����`� �0�賭?Gv����s�m<׬ ��˔�f��^'i腽�ٞ�?�1�ɦ�*�a�<$�H��9��{�������T.��/�c�G�F4۫ܭ��K߳Ŏ���w�hV�����b�X�J�:5�ɟ,����$]�����߻|3x����y�+wG�p�%�V�����څ�r�~\�Q��%��չYѥ HH�*�1MS���Z�HJ��� P�6(�T))�@%H��!Q,L�h�q�P�U*˕U��<.��>#B�e ����:+�M���F��\��X� xK H¦SmK��֧,��[��,Rk�u��{.��5����@!@ �n?h�)Sm�x�(Zi�ܒ� VZB* Z��?/r?i���X0�"����t��y��F?N'��r\�.��c7UmN��a{ ���<�YF7 aZl'<�v�SO�w����ixރ^�v����޶}۽ҹ�Ci\J�^�:�h�g�5k,�>�X���/�ෂۅBBR�V���ɴV�� KLiN�]e#�@91�۷l�2�4�R�Ay�cuos�4.Y�|�"�\Mf����ku2��N<<�ޓ�?��H�ok#�&���@r ��(8���+N=ƴ4T묝�G%�ڨ}W���ݩ�NsH�Q5m��o|��ä́� ���ݑݚ�,V�L��5�9�c�����tn��\#2{�5�~T\98e�;z8��>�N��r�b� ��as#K6qB J������{��֣$#"�vYu^�YM��B�g��w��[�EB�@BHUEz�I��;@��H1�O�B���+Zi[C�?�w��`�B�{}���A�@7�P�@4���ɒ�r�d�D\Ƽ6[v�c�T V��s�*+te����Xk�r�f����������� hoXt��v{��{�q�Z|���)����-�y��� ����������鈕��)�� q:SQ$��5��8c�x���E�„l$� m/�J�"��Z�֙���1܆�oV�ު��N�J^+��z�:�����gY٭n�Vz���_�ӄ�+�����n��I,�[o����� Y��5��\m�b��1/cĮ��1� sh�I�Գ����.�Թw�n�K���Wڻ���XGS�:�\cv�-��%gYtV�&�v �rc��Gy[���U�5��.�4pc��M� �Fgvc h��G�FG�޹p۴u���۷kZ�V�������Q�u��S��ҧ�i����[��)~�ޏ_��Z�~>2��N���S?[O ��y�jk��8�lƮ|���#���T]lт'{�X��E�@{����c���dk:�M� ��|6Ԧb6QX��! �!*D��Ui�*�, R!eVXj�0�R�t�BsR�Q��FS��#=���}A]��Ϣٱ���w��%罽��QB� u��� -�x�(Zm}��ђ*��ڢ�9"Kȼ���q�q�-.<�W17q�����j�2V�������ǀ}��w�9��Nfh��ƃ̯?5�v�&ݭ����/�` g�<�Ȟ�qh�(�s��� �Q�M&~���q���.{ޱ;Gp�\J�N��z��G��}�:��Ē7���Ի+�i�(ro����6��(�RP`�4�����:�h�f� ��Z䫎� �-�g���8��~ �����q�ʮYLq�9,��Ӏ�FPǍݧ?2v-;4 ����$�gz��g m5�����V�c#Ŗ[�T�u=�YV�mq&�qZeb�08 w��RX�t�����mܝ�( iy��#0ѫ��֛M+��7X/�6��V�5�2�=�8�F Iߏ%cGC� ���м�������i�oX�M�aROy����vn.Y�����ol���f������ra��c�Ifsy����p���pW肼�e�w^�p��PT�N[�XY.���i��&�����8+V;[%e���� � Yi��vEH�é�� �S�0���+�Ll������i���M%�Xv:R+��^Y�@ޖ���!���Ni�/���4d��T$�@�M��ȣ�n�"��0斜������h�̔ޕ�i]u��%�7��� ����|�:���+xr���sϋ ���0�#�ˢ���@��,;�1�cZoґ���Z�WmV[�1�rD潍����o4���M֍�Ecv����_�q��g�(h��#� �X����A1a]s�3�U�,f�M�1��ch{��\��s�vF e��u���Q�7o�W.|򚩏���6� �ݩoi�P��p{Mx�,��@�flvGL�5βFe��ը5ִ����(��Ȭ�˖V���?�"�w�c��d��#�|�����GZ��9�vx��������/�X�+ a%��^>AX�[�ȥ�[�ȫy���x0�����D"7�q8��>��7��A sZ^{�n_-�ڇ�� �¸��'ZݾE'ZݾE\���j��a��= �kv�u���Wd� D�����$0ct1{�ɣd id���..�h$�p��YQ�<��hq���f�N�uQ\f�9]E���B\��<������ �V�e�ȠJݾEzdy�=7�n�"���|�!h�����ȣ�n�"�?Ih+5�Rx"�{�/��x�;L}��٤|S]Yb>=��W�u���Q}�|����n��΋�`�pVF�"��0�������+Mtf�k��]������Ϊ̇��$+�4�с�$��������y���HX�C����*�y�E�v+%H��R�$����Z�FBUWaP����~G���=�*�,BT�ZTX�෋5"�GjNs���R��A�'ih?����Ay��DB���X�ʏ?�!����Bm��Šz/�_ ���%���A�[��;����� N���